SDAA403 June   2026 TIC12400-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Polling Mode Operation
    1. 2.1 Polling Cycle Architecture
    2. 2.2 Polling Timing Parameters
    3. 2.3 Register Update Behavior During a Polling Cycle
    4. 2.4 Device Startup Sequence and First Polling Cycle
  6. 3/INT Pin Leakage Current and Interrupt Handling
    1. 3.1 /INT Pin Leakage Specification
    2. 3.2 Interrupt Generation and Configuration
    3. 3.3 Startup Interrupt Behavior and Wakeup Signal Timing
  7. 4Summary
  8. 5References

2.4 Device Startup Sequence and First Polling Cycle

After a device reset (hardware or software), the TIC12400-Q1 does not begin polling autonomously. The host microcontroller must first configure all required registers, then set the TRIGGER bit in the CONFIG register to logic 1. The device will start the first polling cycle 200–400 μs after the TRIGGER bit is set.

The startup sequence is as follows:

Step Action Notes
1 Apply power; wait for device POR to complete Verify VS and VDD are within specification before proceeding.
2 Configure all channel and threshold registers via SPI Set channel mode (ADC or Comparator), wetting current level, polling period, and interrupt configuration.
3 Set TRIGGER bit = 1 in CONFIG register This activates wetting current and initiates the polling cycle timer.
4 Wait Tₛᵗᵃʳᵗ (200–400 μs) for first polling cycle to begin No valid ADC or comparator data is available until the first complete polling cycle has finished.
5 Wait for /INT assertion signaling end of first complete cycle The /INT pin is asserted at the end of the first full polling cycle to indicate that baseline switch states have been captured. Valid data can be read from the ADC_STATx and SWITCH_STATx registers after this point.

Table 3. TIC12400-Q1 Device Startup Sequence

NOTE: The TIC12400-Q1 interrupt is state-change based, not edge-triggered. The "state" established at the end of the first polling cycle becomes the baseline for all subsequent interrupt comparisons. If an input has already transitioned to its active state before the first polling cycle completes, that active state will be stored as the baseline and no interrupt will be generated for that transition.