4 Summary

The TIC12400-Q1 polling cycle consists of three sequential phases: wetting current activation, channel-by-channel sampling, and an idle period. Wetting current is only active during the first phase and is off for the remainder of the interval. The polling period timer runs independently of the number of enabled channels, so reducing the active channel count lengthens the idle phase without changing the programmed period.

Each INx channel's result register is updated immediately after that channel is sampled, not at the end of the full cycle. A SPI read performed mid-cycle will therefore return a mix of current-cycle and previous-cycle values depending on where in the sequence the read falls. Register bits designated type RC are cleared on read; type R bits retain their value.

The device does not begin polling after reset until the host sets the TRIGGER bit in the CONFIG register. The first polling cycle starts 200–400 μS after that bit is set. The /INT pin is asserted at the end of the first complete cycle to signal that a valid baseline state has been captured. Because the interrupt system is state-change based, any input that is already in its active state when the first cycle completes will be stored as baseline and will not produce an interrupt for that initial transition. Applications with strict wakeup detection requirements should read the SWITCH_STATx registers after the first /INT assertion rather than relying on interrupt generation alone.

The /INT pin leakage current is specified at ±1 μA maximum (ATE-verified, pin pulled to VDD). This is not a risk for spurious interrupt triggering and should not be confused with the INx pin leakage specification of ±110 μA, which is a separate parameter applying to the input channels only.