SDAA403 June   2026 TIC12400-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Polling Mode Operation
    1. 2.1 Polling Cycle Architecture
    2. 2.2 Polling Timing Parameters
    3. 2.3 Register Update Behavior During a Polling Cycle
    4. 2.4 Device Startup Sequence and First Polling Cycle
  6. 3/INT Pin Leakage Current and Interrupt Handling
    1. 3.1 /INT Pin Leakage Specification
    2. 3.2 Interrupt Generation and Configuration
    3. 3.3 Startup Interrupt Behavior and Wakeup Signal Timing
  7. 4Summary
  8. 5References

3.1 /INT Pin Leakage Specification

The /INT pin is an active-low, open-drain output. It is normally held high by an external pull-up resistor connected to VDD and pulled low by the TIC12400-Q1 to assert an interrupt.

A common application concern is whether leakage current on the /INT pin could cause spurious triggering when the pin is in the de-asserted (high) state. The relevant datasheet parameter is the /INT output leakage current, tested with /INT pulled up to VDD:

Parameter Min Max Unit
/INT output leakage current (pin pulled up to VDD) −1 +1 μA

Table 4. /INT Pin Leakage Current Specification

The ±1 μA specification is a passing ATE parameter. In practice, the leakage current on the /INT pin is well within this range and is not a source of spurious interrupt triggering under normal operating conditions. The leakage current is three orders of magnitude smaller than the INx pin leakage (up to ±110 μA) and should not be confused with it.

NOTE: The ±110 μA leakage specification applies to the INx input pins only, not to the /INT output pin. These two specifications are independent and serve different design purposes.