SDAA503 September   2026 F29H850TU

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Pierce Oscillator and Crystal Model
    1. 2.1 Oscillator Block Diagram
    2. 2.2 Quartz Crystal Electrical Model
  6. 3 Crystal Selection Criteria
    1. 3.1 Why ESR Governs Crystal Compatibility
    2. 3.2 Crystal Frequency
    3. 3.3 Shunt Capacitance C0
  7. 4 Step-by-step Crystal Selection Process
    1. 4.1 Step 1 - Verify ESR Meets Oscillator Requirements
    2. 4.2 Step 2 - Size Load Capacitors CL1 and CL2
    3. 4.3 Step 3 - Determine if Damping Resistor Rd is Required
    4. 4.4 Step 4 - Calculate Rd (Damping Resistor)
    5. 4.5 Step 5 - Verify Negative Resistance (Rneg) Margin
  8. 5 PCB Layout Recommendations
    1. 5.1 Crystal Placement
    2. 5.2 Load Capacitor Placement
    3. 5.3 Trace Routing
    4. 5.4 Shielding Considerations
  9. 6 Testing and Validation
    1. 6.1 Measurement Equipment Requirements
    2. 6.2 Frequency Verification
    3. 6.3 Start-Up Time Measurement
    4. 6.4 Negative Resistance (Rneg) Measurement
  10. 7 Common Issues and Debug Tips
  11. 8 Design Example - 20MHz Crystal
  12. 9 Appendix A
    1. 9.1 Crystal Selection for Generic Pierce Oscillators
      1. 9.1.1 Introduction and Scope
      2. 9.1.2 Theoretical Background
      3. 9.1.3 Method A - Analytical Derivation from gm_min
        1. 9.1.3.1 Equipment and Component Requirements
        2. 9.1.3.2 Procedure
        3. 9.1.3.3 Single-Frequency Oscillator Considerations
        4. 9.1.3.4 Worked Example — 40MHz Fixed-Frequency Oscillator
      4. 9.1.4 Method B - Empirical Derivation using Negative Resistance Test
        1. 9.1.4.1 Equipment and Component Requirements
        2. 9.1.4.2 Signal Generator as Crystal Substitute
        3. 9.1.4.3 Equations
        4. 9.1.4.4 Procedure
        5. 9.1.4.5 Alternative Experimental Methods for Deriving gm
          1. 9.1.4.5.1 Load Capacitance (CL) Sweep
          2. 9.1.4.5.2 Supply Voltage (VDD) Sweep
          3. 9.1.4.5.3 Temperature Sweep (Thermal Margin Identification)
        6. 9.1.4.6 Generating a Custom ESR/CL Requirement Table
      5. 9.1.5 Method C - Frequency Pulling Characterization
        1. 9.1.5.1 Required Equipment and Components
        2. 9.1.5.2 Equations
        3. 9.1.5.3 Procedure
        4. 9.1.5.4 Worked Example - 40MHz Frequency Pulling
      6. 9.1.6 Summary Checklist - Generic Pierce Oscillator Crystal Selection
  13. 10References
9.1.4.5.2 Supply Voltage (VDD) Sweep

CMOS inverter gm decreases as VDD is reduced and as temperature increases. The VDD sweep identifies the supply voltage at which the oscillator just fails, giving gm at that corner.

Equipment required: Adjustable low-noise DC supply, XCLKOUT frequency counter, optional temperature chamber.

  1. Set temperature to maximum operating temperature (T_max) if a chamber is available. Otherwise test at room temperature — results will be optimistic.
  2. With production CL1 = CL2 installed, set VDD to nominal. Confirm oscillation.
  3. Reduce VDD slowly (1mV/s to 5mV/s). Monitor XCLKOUT for loss of oscillation.
  4. Record VDD_crit: the supply voltage at which oscillation stops.
  5. At VDD_crit the margin = 1, so:
Equation 31. gm(VDD_crit, T) = ESR × ω²×CL_design²

Because VDD_min > VDD_crit by design, the oscillator has margin. A first-order estimate of the margin at VDD_min uses the linear gm–VDD relationship (valid for short-channel CMOS in saturation):

Equation 32. Margin_est ≅ gm(VDD_min) / gm(VDD_crit) ≅ VDD_min / VDD_crit
Note:

Equation 32 is a conservative first-order approximation. Actual gm–VDD scaling depends on the process node and operating region (saturation versus subthreshold). For a definitive gm_min, combine this measurement with the Rx sweep (Section 6.4) at VDD_min and T_max simultaneously.