SDAA503 September   2026 F28E120SB , F28E120SC , F29H850DM , F29H850TU , F29H859TU-Q1 , F29P329SM-Q1 , F29P589DM-Q1 , F29P589DU-Q1 , TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P551SG , TMS320F28P559SG-Q1 , TMS320F28P559SJ-Q1 , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Pierce Oscillator and Crystal Model
    1. 2.1 Oscillator Block Diagram
    2. 2.2 Quartz Crystal Electrical Model
  6. 3 Crystal Selection Criteria
    1. 3.1 Why ESR Governs Crystal Compatibility
    2. 3.2 Crystal Frequency
    3. 3.3 Shunt Capacitance C0
  7. 4 Step-by-step Crystal Selection Process
    1. 4.1 Step 1 - Verify ESR Meets Oscillator Requirements
    2. 4.2 Step 2 - Size Load Capacitors CL1 and CL2
    3. 4.3 Step 3 - Determine if Damping Resistor Rd is Required
    4. 4.4 Step 4 - Calculate Rd (Damping Resistor)
    5. 4.5 Step 5 - Verify Negative Resistance (Rneg) Margin
  8. 5 PCB Layout Recommendations
    1. 5.1 Crystal Placement
    2. 5.2 Load Capacitor Placement
    3. 5.3 Trace Routing
    4. 5.4 Shielding Considerations
  9. 6 Testing and Validation
    1. 6.1 Measurement Equipment Requirements
    2. 6.2 Frequency Verification
    3. 6.3 Start-Up Time Measurement
    4. 6.4 Negative Resistance (Rneg) Measurement
  10. 7 Common Issues and Debug Tips
  11. 8 Design Example - 20MHz Crystal
  12. 9 Appendix A
    1. 9.1 Crystal Selection for Generic Pierce Oscillators
      1. 9.1.1 Introduction and Scope
      2. 9.1.2 Theoretical Background
      3. 9.1.3 Method A - Analytical Derivation from gm_min
        1. 9.1.3.1 Equipment and Component Requirements
        2. 9.1.3.2 Procedure
        3. 9.1.3.3 Single-Frequency Oscillator Considerations
        4. 9.1.3.4 Worked Example — 40MHz Fixed-Frequency Oscillator
      4. 9.1.4 Method B - Empirical Derivation using Negative Resistance Test
        1. 9.1.4.1 Equipment and Component Requirements
        2. 9.1.4.2 Signal Generator as Crystal Substitute
        3. 9.1.4.3 Equations
        4. 9.1.4.4 Procedure
        5. 9.1.4.5 Alternative Experimental Methods for Deriving gm
          1. 9.1.4.5.1 Load Capacitance (CL) Sweep
          2. 9.1.4.5.2 Supply Voltage (VDD) Sweep
          3. 9.1.4.5.3 Temperature Sweep (Thermal Margin Identification)
        6. 9.1.4.6 Generating a Custom ESR/CL Requirement Table
      5. 9.1.5 Method C - Frequency Pulling Characterization
        1. 9.1.5.1 Required Equipment and Components
        2. 9.1.5.2 Equations
        3. 9.1.5.3 Procedure
        4. 9.1.5.4 Worked Example - 40MHz Frequency Pulling
      6. 9.1.6 Summary Checklist - Generic Pierce Oscillator Crystal Selection
  13. 10References

5.2 Load Capacitor Placement

  • Place CL1 and CL2 immediately adjacent to the X1 and X2 pins, respectively, with the ground terminal of each capacitor connected directly to the local ground pour. Do not share a single ground via between both capacitors - each must have its own via.
  • Keep CL1 and CL2 traces as short and direct as possible. Route them on a single layer without bends or vias between the device pin and the capacitor pad.
  • Use C0G/NP0 capacitors for CL1 and CL2.