SDAA503 September   2026 F29H850TU

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Pierce Oscillator and Crystal Model
    1. 2.1 Oscillator Block Diagram
    2. 2.2 Quartz Crystal Electrical Model
  6. 3 Crystal Selection Criteria
    1. 3.1 Why ESR Governs Crystal Compatibility
    2. 3.2 Crystal Frequency
    3. 3.3 Shunt Capacitance C0
  7. 4 Step-by-step Crystal Selection Process
    1. 4.1 Step 1 - Verify ESR Meets Oscillator Requirements
    2. 4.2 Step 2 - Size Load Capacitors CL1 and CL2
    3. 4.3 Step 3 - Determine if Damping Resistor Rd is Required
    4. 4.4 Step 4 - Calculate Rd (Damping Resistor)
    5. 4.5 Step 5 - Verify Negative Resistance (Rneg) Margin
  8. 5 PCB Layout Recommendations
    1. 5.1 Crystal Placement
    2. 5.2 Load Capacitor Placement
    3. 5.3 Trace Routing
    4. 5.4 Shielding Considerations
  9. 6 Testing and Validation
    1. 6.1 Measurement Equipment Requirements
    2. 6.2 Frequency Verification
    3. 6.3 Start-Up Time Measurement
    4. 6.4 Negative Resistance (Rneg) Measurement
  10. 7 Common Issues and Debug Tips
  11. 8 Design Example - 20MHz Crystal
  12. 9 Appendix A
    1. 9.1 Crystal Selection for Generic Pierce Oscillators
      1. 9.1.1 Introduction and Scope
      2. 9.1.2 Theoretical Background
      3. 9.1.3 Method A - Analytical Derivation from gm_min
        1. 9.1.3.1 Equipment and Component Requirements
        2. 9.1.3.2 Procedure
        3. 9.1.3.3 Single-Frequency Oscillator Considerations
        4. 9.1.3.4 Worked Example — 40MHz Fixed-Frequency Oscillator
      4. 9.1.4 Method B - Empirical Derivation using Negative Resistance Test
        1. 9.1.4.1 Equipment and Component Requirements
        2. 9.1.4.2 Signal Generator as Crystal Substitute
        3. 9.1.4.3 Equations
        4. 9.1.4.4 Procedure
        5. 9.1.4.5 Alternative Experimental Methods for Deriving gm
          1. 9.1.4.5.1 Load Capacitance (CL) Sweep
          2. 9.1.4.5.2 Supply Voltage (VDD) Sweep
          3. 9.1.4.5.3 Temperature Sweep (Thermal Margin Identification)
        6. 9.1.4.6 Generating a Custom ESR/CL Requirement Table
      5. 9.1.5 Method C - Frequency Pulling Characterization
        1. 9.1.5.1 Required Equipment and Components
        2. 9.1.5.2 Equations
        3. 9.1.5.3 Procedure
        4. 9.1.5.4 Worked Example - 40MHz Frequency Pulling
      6. 9.1.6 Summary Checklist - Generic Pierce Oscillator Crystal Selection
  13. 10References

2.1 Oscillator Block Diagram

The on-chip Pierce oscillator consists of a CMOS inverter amplifier whose output is fed back to the input through the crystal tank circuit. Two external load capacitors (CL1 and CL2) are connected from X1 and X2 to ground. An optional series damping resistor Rd is placed between X2 and the crystal when drive level must be reduced. Figure 2-1 shows the complete circuit topology.

Simplified Pierce Oscillator Circuit With External Components Figure 2-1 Simplified Pierce Oscillator Circuit With External Components