SDAA545 October   2026 AM2752-Q1 , AM2754-Q1 , AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1 , AM62L , AM62P , AM62P-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Understanding the Purpose of DMA
    2. 1.2 How does DMA work?
    3. 1.3 Why CDD DMA?
    4. 1.4 CDD Module Placement in the AUTOSAR BSW Stack
  5. 2Types of DMA
    1. 2.1 Block Copy DMA (BCDMA)
      1. 2.1.1 BCDMA Software Flow
    2. 2.2 Packet DMA – Peripheral TX (PKTDMA-TX)
    3. 2.3 Packet DMA – Peripheral RX (PKTDMA-RX)
      1. 2.3.1 PKTDMA Software Flow
    4. 2.4 Polling Mode Versus Interrupt Mode
    5. 2.5 DMA Channel Chaining
  6. 3Hardware Architecture: Inside the DMA Factory
    1. 3.1 Ring Accelerator (RINGACC)
      1. 3.1.1 Key Characteristics
    2. 3.2 Packet Streaming Interface Link (PSIL)
      1. 3.2.1 Key Characteristics
    3. 3.3 Descriptors: [TRPD and HPD]
      1. 3.3.1 Transfer Request Packet Descriptor (TRPD) - For Memory-to-Memory Moves
      2. 3.3.2 Host Packet Descriptor (HPD) - For Peripheral Communications
    4. 3.4 Interrupt Aggregator
      1. 3.4.1 Key Characteristics
  7. 4Software Overview
    1. 4.1 Three-Layer Driver Architecture
      1. 4.1.1 API Layer
        1. 4.1.1.1 Key Responsibilities
      2. 4.1.2 Private Layer
        1. 4.1.2.1 Key Responsibilities
      3. 4.1.3 Low-Level Driver
        1. 4.1.3.1 Key Responsibilities:
    2. 4.2 Memory Requirements
    3. 4.3 AUTOSAR Integration
      1. 4.3.1 Schedule Manager (SchM) Integration
      2. 4.3.2 Development Error Tracer (DET)
      3. 4.3.3 ECU Manager (EcuM) Integration and Boot Sequence
      4. 4.3.4 AUTOSAR OS vs FreeRTOS - ISR Category Configuration
      5. 4.3.5 Memory Protection Unit (MPU) Considerations for DMA Buffers
      6. 4.3.6 Inter-Module AUTOSAR Dependencies and Initialization Order
  8. 5Use Cases
    1. 5.1 Flash Copy with DMA
      1. 5.1.1 Flash DMA Overview
      2. 5.1.2 How DMA Enhances Flash Performance
      3. 5.1.3 Initialization Sequence
      4. 5.1.4 Constraints and Fallback Behavior
    2. 5.2 Use Case: Amplifier Data Transmission Using CDD UART With DMA
      1. 5.2.1 UART DMA Overview
      2. 5.2.2 How DMA Enhances Amplifier Data Throughput
      3. 5.2.3 Initialization Sequence
  9. 6Step-by-Step Guide to Write a CDD DMA Application
    1. 6.1 Step 1 - Configure EB Tresos
    2. 6.2 Step 2 - Allocate Memory (128-Byte Aligned, in DDR)
    3. 6.3 Step 3 - Initialize the Driver
    4. 6.4 Step 4 - Open and Enable the Channel
    5. 6.5 Step 5 - Submit the Transfer
    6. 6.6 Step 6 - Wait for Completion
    7. 6.7 Step 7 - Clean Up
    8. 6.8 Common Mistakes to Avoid
  10. 7Summary
  11. 8References
    1. 8.1 Example Applications (in MCAL):

3.1.1 Key Characteristics

  • Dual Queue System: Each DMA channel manages two logical queues
  • Free Queue (FQ): Contains pointers to descriptors ready for work
  • Completion Queue (CQ): Contains pointers to completed descriptors with results
  • Automatic Management: Hardware handles queue pointer updates - no CPU intervention needed for basic operations
  • Memory Efficient: Queue elements are simply 64-bit pointers to descriptor memory
  • Cache Optimized: All ring memory must be 128-byte cache line aligned for best performance

The typical ring interaction for a Block Copy transfer is shown in Figure 3-2:


Ring Accelerator Interaction Flow

Figure 3-1 Ring Accelerator Interaction Flow
Note: Ring memory must be allocated in DDR and must be 128-byte cache-line aligned. Misalignment causes silent data corruption. Each ring element is eight bytes (a 64-bit descriptor pointer).

Ring Accelerator (RINGACC) Descriptor Flow Between Free Queue, DMA Engine, and Completion Queue

Figure 3-2 Ring Accelerator (RINGACC) Descriptor Flow Between Free Queue, DMA Engine, and Completion Queue