SLAAE75B March   2023  – May 2023 MSPM0L1105 , MSPM0L1106 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 MSPM0L Hardware Design Checklist
  5. 2 Power Supplies in MSPM0L Devices
    1. 2.1 Digital Power Supply
    2. 2.2 Analog Power Supply
    3. 2.3 Built-in Power Supply and Voltage Reference
    4. 2.4 Recommended Decoupling Circuit for Power Supply
  6. 3 Reset and Power Supply Supervisor
    1. 3.1 Digital Power Supply
    2. 3.2 Power Supply Supervisor
  7. 4 Clock System
    1. 4.1 Internal Oscillators
    2. 4.2 External Clock Output (CLK_OUT)
    3. 4.3 Frequency Clock Counter (FCC)
  8. 5 Debugger
    1. 5.1 Debug Port Pins and Pinout
    2. 5.2 Debug Port Connection With Standard JTAG Connector
  9. 6 Key Analog Peripherals
    1. 6.1 ADC Design Considerations
    2. 6.2 OPA Design Considerations
    3. 6.3 DAC Design Considerations
    4. 6.4 COMP Design Considerations
    5. 6.5 GPAMP Design Considerations
    6. 6.6 LCD Design Considerations
  10. 7 Key Digital Peripherals
    1. 7.1 Timer Resources and Design Considerations
    2. 7.2 UART and LIN Resources and Design Considerations
    3. 7.3 I2C and SPI Design Considerations
  11. 8 GPIOs
    1. 8.1 GPIO Output Switching Speed and Load Capacitance
    2. 8.2 GPIO Current Sink and Source
    3. 8.3 High Speed GPIOs
    4. 8.4 Open-Drain GPIOs Enable 5-V Communication Without a Level Shifter
    5. 8.5 Communicate With 1.8V Devices Without a Level Shifter
    6. 8.6 Unused Pins Connection
  12. 9 Layout Guides
    1. 9.1 Power Supply Layout
    2. 9.2 Considerations for Ground Layout
    3. 9.3 Traces, Vias, and Other PCB Components
    4. 9.4 How to Select Board Layers and Recommended Stack-up
  13. 10Bootloader
    1. 10.1 Bootloader Introduction
    2. 10.2 Bootloader Hardware Design Considerations
      1. 10.2.1 Physical Communication interfaces
      2. 10.2.2 Hardware Invocation
  14. 11References
  15. 12Revision History

6.6 LCD Design Considerations

The Liquid Crystal Display (LCD) controller on MSPM0L directly drives LCD displays through segment (SEG) and COM voltage signals. This controller can support static and 2-mux to 8-mux mode LCD segment displays.

This section only discusses the key considerations on schematic and PCB design. For more instruction on the LCD design, see Designing With MSPM0™ MCUs and Segment LCDs.

For the schematic design, the LCD controller can directly drive the LCD without requiring additional components in common use cases. However, when utilizing a charge pump to generate a constant voltage (especially if VDD is battery-powered to prevent display fluctuations caused by VDD voltage variations), capacitors at LCDCAP0/1 and resistors R13, R24, R23, R33 can be required, as shown in Figure 6-10.

LCD Capacitor Setting When using Charge Pump Figure 6-10 LCD Capacitor Setting When using Charge Pump

For the PCB design, here are the general layout rules:

LCD signal lines are constantly switching to keep the image on the display, keep them away from noise-sensitive lines (such as the external crystal connections). Use guard rings to shield noise-sensitive lines, such as the crystal connections or ADC inputs, from noise coupling. A ground plane underneath the LCD traces and guard traces also provide shielding. One good practice is to keep all LCD signal traces (segment and common lines) together, similar to a data bus. Keeping the LCD layout in a single layer is helpful so that there are not LCD traces running over or under potentially sensitive traces. Keep the charge pump capacitor on the LOADCAP pin as close as possible to the MCU with a short trace.