SLAAEE7A September   2024  – August 2025 MSPM0C1105 , MSPM0C1106 , MSPM0G1106 , MSPM0G1107 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0H3216

 

  1.   1
  2. 1 Description
  3. 2 Required Peripherals
  4. 3 Design Steps
  5. 4 Design Considerations
  6. 5 Software Flow Chart
  7. 6 Design Results
  8. 7 Reference
  9. 8 E2E
  10. 9 Revision History
  11. 10Trademarks

1 Description

The power sequencing example demonstrates turning on multiple rails from one start-up, at different intervals. This precaution helps prevent damaging devices during start-up that causes power spikes, bus contention, latch-up errors, and other issues. The MSPM0 allows for use of only one timer to set different intervals for each rail.

MSPM0G3507 Subsystem Functional Block DiagramFigure 1-1 Subsystem Functional Block Diagram