SLAAEG6A November   2023  – September 2024 TAA5212 , TAA5242 , TAA5412-Q1 , TAC5111 , TAC5111-Q1 , TAC5112 , TAC5112-Q1 , TAC5142 , TAC5211 , TAC5212 , TAC5212-Q1 , TAC5242 , TAC5301-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5112 , TAD5112-Q1 , TAD5142 , TAD5212 , TAD5212-Q1 , TAD5242

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Operating Modes for the Clocking
    1. 2.1 Automatic Modes of Operation
  6. 3Clocking Modes
    1. 3.1 Auto Primary BCLK Ratio
    2. 3.2 Auto Secondary BCLK Ratio
    3. 3.3 Auto MCLK Ratio
    4. 3.4 Auto MCLK Fixed
    5. 3.5 Custom Mode and Semi Automatic Mode of Operation
      1. 3.5.1 Semi-Automatic Mode
    6. 3.6 Additional Clocks
      1. 3.6.1 PDM Clocks
      2. 3.6.2 Boost Clock
      3. 3.6.3 SAR Clock
      4. 3.6.4 CLKOUT
  7. 4Clocking in Hardware Controlled Devices
  8. 5Revision History

1 Introduction

The Device Supports a Primary as well as Secondary ASI. There are several automatic modes of operation described where either the primary BCLK /FYSNC or Secondary BCLK/FSYNC can be used for determination of the incoming timing modes.

In addition, the MCLK / FSYNC can also be used to do the timing determination.

The device has the following interfaces that setup the clocking.

Interface Setup
MCLK Master Clock
FSYNC Primary FSYNC/ Secondary SYNC
PASI BCLK Primary BCLK
PASI FSYNC Primary FSYNC
SASI BCLK Secondary BCLK
SASI FSYNC Secondary SYNC

The BCLK and FSYNC Pins as well as the GPIO/GPI/GPO pins can be configured to setup the Primary and Secondary ASI.

The timings must lie within the limits described in Table 1-1 and Table 1-2.

Table 1-1 Multiples of 48Khz
Pins Timings
Fs 3KHz-768KHz
BCLK 256KHz - 24.576MHz
MCLK 256KHz - 49.152MHz
Table 1-2 Multiples of 44.1Khz
Pins Timings
Fs 2.75KHz-705.6KHz
BCLK 235.2KHz – 22.57MHz
MCLK 235.1KHz - 45.15MHz
Note: The nomenclature of Target is used to indicate Slave Mode of Operation. The nomenclature of Controller is used to indicate Master Mode of operation.