SLAAEO8A October   2024  – November 2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0C1105 , MSPM0C1106 , MSPM0C1106-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0H3216 , MSPM0H3216-Q1 , MSPM0L1105

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1ADC Introduction
    1. 1.1 SAR ADC Principle
    2. 1.2 ADC Parameters
      1. 1.2.1 Static Parameters
      2. 1.2.2 Dynamic Parameters
        1. 1.2.2.1 AC Parameters
        2. 1.2.2.2 DC Parameters
  5. 2ADC Noise Analysis
    1. 2.1 ADC Noise Classification
      1. 2.1.1 ADC Noise
      2. 2.1.2 Reference Noise
      3. 2.1.3 Power Supply Noise
      4. 2.1.4 ADC Input Noise
      5. 2.1.5 Clock Jitter
    2. 2.2 How to Reduce Noise
      1. 2.2.1 Reducing Input Noise Through RC Filtering
      2. 2.2.2 Layout Suggestions
      3. 2.2.3 Improving Signal-to-Noise Ratio
      4. 2.2.4 Choose a Suitable Reference Voltage Source
      5. 2.2.5 Software Methods for Reducing Noise
  6. 3ADC Oversampling
    1. 3.1 Sampling Rate
    2. 3.2 Extraction
    3. 3.3 Application Conditions
  7. 4ADC Application Based on MSPM0
    1. 4.1 ADC Configuration of MSPM0
    2. 4.2 ADC DC Test Based on MSPM0G3507 ADC EVM Board
      1. 4.2.1 Software/Hardware Configuration
        1. 4.2.1.1 Hardware
        2. 4.2.1.2 Software
      2. 4.2.2 Test Result
      3. 4.2.3 Result Analysis and Conclusion
  8. 5Revision History

4.1 ADC Configuration of MSPM0

  • Clock
    ADC Clock Sysconfig ConfigurationFigure 4-1 ADC Clock Sysconfig Configuration
    • ADC Clock（ADCCLK）
      • SYSOSC（max 32MHz）
      • HFCLK（max 48MHz）
      • ULPCLK（max 40MHz, PD0）
    • ADC Sampling Clock（SAMPCLK）：divided by ADCCLK
    • Conversion Clock（Conversion clock）：ADC IP internal 80MHz crystal oscillator
      • The conversion time for 12-bit ADC data is approximately 14 conversion clock cycles
  • Sampling mode
    ADC Sampling Mode Sysconfig ConfigurationFigure 4-2 ADC Sampling Mode Sysconfig Configuration
  • Conversion mode
    • Single conversion: Only a single point is converted during each sampling and conversion process, and the MEMCTL number used is determined by configuring the conversion start address STARTADD;
    • Sequence conversion: By defining the starting address STARTADD and ending address ENDADD of the MEMCTL number used for conversion, a sequence of data conversion can be defined (MEMCTL0-11 corresponds to MEMRES0-11), and ADC channels can be configured separately for each MEMCTLx;
  • Enable repeat mode
    • Non-repetitive mode: After each round of conversion is completed, conversion enable bit (ENC) automatically resets to zero;
    • Repetitive mode: The conversion process will continue to be enabled until the conversion enable bit (ENC) is cleared by the software;
  • Sampling trigger source
    • Software: Software setting CTL1.SC bit trigger sampling;
    • Event: Event rising edge triggering sampling;
  • Sampling mode
    • Automatic sampling: After the sampling trigger signal is generated, the sampling signal SAMPLE is automatically raised, with a sampling time of several SAMPCLK clock cycles defined by SCOMP;
    • Manual sampling (only supports software triggering, does not support repetitive mode and sequence conversion, does not support hardware oversampling): The sampling signal SAMPLE is synchronized pulling up with the software triggering signal CTL1.SC. The sampling time is determined by determining the pulling up time of the SC, and triggering and sampling are completed synchronously;
  • Trigger mode
    • In the repetition and sequence conversion modes, the trigger mode (TRIG) needs to be selected to determine whether the next round of conversion requires a trigger signal.
  • Conversion memory configuration
    ADC Conversion Memory Sysconfig ConfigurationFigure 4-3 ADC Conversion Memory Sysconfig Configuration
  • The amount of conversion memory that needs to be configured is determined by the MEMCTL start and end numbers defined in the conversion mode:
    • Sampling input channel
    • Reference voltage
      • VDDA：Internal power supply (3.3V)
      • VREF
        • Internal：2.5V/1.4V
        • External：0~3.3V

        Sampling Timer Source: Select the timer used for sampling time counting in automatic sampling mode

    • Others
      • Oversampling
        • sampling result multiple = number of sampling points/average denominator
      • Interrupt
        • Not using DMA: enable MEMx result loading interrupt, and read data in the interrupt after each sampling result is generated;
        • Using DMA: Enable DMA completion interrupts, and trigger DMA data transfer based on the ADC MEMx result loading, and set the amount of DMA transfer data. Once the DMA transfer is completed, enter DMA interrupts to process ADC sampling data at once.

      • CPU poll

        • CPU poll MEMx result loading register, corresponding CPU_INT RIS bit is set to 1 when ADC conversion is done and result is loaded into MEMx.
        • CPU poll ADC status register, ADC status busy bit is cleared when ADC conversion is done.
          Note:

          For the device listed below, busy will be set after 14 ULPCLK cycles after ADC start conversion bit is set in CTL1 register. This 14 ULPCLK need to take CPU delay to wait for busy bit set, then CPU can poll the busy bit to wait for busy bit clear. Recommend to use MEMx result loading register to poll the ADC conversion done status.

          MSPM0C110x, L1x0x, L111x, L134x, Lx22x, Gx10x, Gx50x, Gx51x, H321x.