SLAS574B September   2013  – November 2025 ADS5474-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Input Configuration
      2. 6.1.2 Clock Inputs
      3. 6.1.3 Digital Outputs
  8. 7 Application and Implementation
    1. 7.1 Power Supply Recommendations
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Definition of Specifications
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.6 Timing Characteristics

Typical values at TC = 25°C: minimum and maximum values over full temperature range TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 400MSPS, 50% clock duty cycle, AVDD5 = 5V, AVDD3 = 3.3V, DVDD3 = 3.3V, and 3VPP differential clock, unless otherwise noted.
PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT
ta Aperture delay 200 ps
Aperture jitter, rms Internal jitter of the ADC 103 fs
Latency 3.5 cycles
tCLK Clock period 2.5 50 ns
tCLKH Clock pulse duration, high 1 ns
tCLKL Clock pulse duration, low 1 ns
tDRY CLK to DRY delay(2) Zero crossing, 10pF parasitic loading to GND on each output pin 700 1600 2500 ps
tDATA CLK to DATA/OVR delay(2) Zero crossing, 10pF parasitic loading to GND on each output pin 650 1600 2600 ps
tSKEW DATA to DRY skew tDATA – tDRY, 10pF parasitic loading to GND on each output pin -700 0 700 ps
tRISE DRY/DATA/OVR rise time 10pF parasitic loading to GND on each output pin 500 ps
tFALL DRY/DATA/OVR fall time 10pF parasitic loading to GND on each output pin 500 ps
(1) Timing parameters are assured by characterization, but not production tested.
(2) DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the overall propagation delay.
ADS5474-SP Timing Diagram
A. Polarity of DRY is undetermined. For further information, see Section 6.1.3.
Figure 5-2 Timing Diagram