The ADC provides 14 LVDS-compatible, offset binary data outputs (D13 to D0; D13 is the MSB and D0 is the LSB), a data-ready signal (DRY), and an over-range indicator (OVR). TI recommends using the DRY signal to capture the output data of the ADS5474. DRY is source-synchronous to the DATA/OVR outputs and operates at the same frequency, creating a half-rate DDR interface that updates data on both the rising and falling edges of DRY. TI recommends minimizing the capacitive loading on the digital outputs. Higher capacitance shortens the data-valid timing window. The values given for timing (see Figure 5-2) are obtained with a measured 10pF parasitic board capacitance to ground on each LVDS line (or 5pF differential parasitic capacitance). When setting the time relationship between DRY and DATA at the receiving device, TI recommends maximizing setup time, but this time partially depends on the setup and hold times of the device receiving the digital data (such as an FPGA or Field Programmable Field Array). Because DRY and DATA are coincident, TI recommends delaying either DRY or DATA to maximize setup time.

Referencing Figure 5-2, the polarity of DRY with respect to the sample N data output transition is undetermined because of the unknown Startup logic level of the clock divider that generates the DRY signal (DRY is a frequency divide-by-two of CLK). Either the rising or the falling edge of DRY coincide with sample N and the polarity of DRY can invert when power is cycled off and on, or when the power-down pin cycle. Data capture from the transition and not the polarity of DRY is recommended, but not required. If the synchronization of multiple ADS5474 devices is required, it can be necessary to use a form of the CLKIN signal rather than DRY to capture the data.

The DRY frequency is identical on the ADS5474 and ADS5463 (where DRY equals ½ the CLK frequency), but different than it is on the pin-similar ADS5444 (where DRY equals the CLK frequency). The LVDS outputs all require an external 100Ω load between each output pair to meet the expected LVDS voltage levels. For long trace lengths, it may be necessary to place a 100Ω load on each digital output as close to the ADS5474 as possible and another 100Ω differential load at the end of the LVDS transmission line to provide matched impedance and avoid signal reflections. The effective load in this case reduces the LVDS voltage levels by half.

The OVR output equals a logic high when the 14-bit output word attempts to exceed either all 0s or all 1s. This flag is provided as an indicator that the analog input signal exceeded the full-scale input limit of approximately 2.2V_PP (± gain error). The OVR indicator is provided for systems that use gain control to keep the analog input signal within acceptable limits.