Drive the ADS5474 clock input with either a differential clock signal or a single-ended clock input. The characterization of the ADS5474 is typically performed with a 3V_PP differential clock, but the ADC perfoRMS well with a differential clock amplitude down to ≅0.5V_PP. The clock amplitude becomes more of a factor in performance as the analog input frequency increases. In low-input-frequency applications, where jitter may not be a big concern, the use of a single-ended clock can save cost and board space without much performance tradeoff. When clocked with this configuration, TI recommends connecting CLK to ground with a 0.01μF capacitor, while CLK is AC-coupled with a 0.01μF capacitor to the clock source, as shown in Figure 6-6.

Figure 6-5 Clock Input Circuit

Figure 6-6 Single-Ended Clock

For jitter-sensitive applications, the use of a differential clock has some advantages at the system level. The differential clock allows for common-mode noise rejection at the printed circuit board (PCB) level. With a differential clock, the signal-to-noise ratio of the ADC is better for jitter-sensitive, high-frequency applications because the board level clock jitter is best.

Larger clock amplitude levels are recommended for high analog input frequencies or slow clock frequencies. In the case of a sinusoidal clock, larger amplitudes result in higher clock slew rates and reduces the impact of clock noise on jitter. At high analog input frequencies, the sampling process is sensitive to jitter. At slow clock frequencies, a small amplitude sinusoidal clock has a lower slew rate and can create jitter-related SNR degradation. Figure 6-7 demonstrates a recommended method for converting a single-ended clock source into a differential clock. The method is similar to the configuration found on the evaluation board and was used for much of the characterization. See the Clocking High Speed Data Converters analog design journal for more details.

Figure 6-7 Differential Clock

The common-mode voltage of the clock inputs is set internally to 2.4V using internal 1kΩ resistors. TI recommends using AC coupling. If AC coupling is not possible, the ADS5474 features good tolerance to clock common-mode variation. Additionally, the internal ADC core uses both edges of the clock for the conversion process. An excellent choice is a 50% duty-cycle clock signal.

The ADS5474 is capable of achieving 69.2dBFS SNR at 350MHz of analog input frequency. To achieve the SNR at 350MHz, verify that the clock source RMS jitter is at least 144fs for the total RMS jitter to be 177fs. A summary of maximum recommended RMS clock jitter as a function of analog input frequency is provided in Table 6-1. Equation 1 and Equation 2 used in creating the table are below.

Use Equation 1 and Equation 2 to estimate the required clock source jitter.

where

• j_TOTAL = RMS summation of the clock and ADC aperture jitter
• ƒ_IN = analog input frequency
• j_ADC = ADC internal aperture jitter, located in the data sheet
• j_CLOCK = RMS jitter of the clock at the clock input pins to the ADC

The SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates. For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC Devices application note. Recommended clock distribution chips (CDCs) are the TI CDC7005, the CDCM7005-SP and CDCE72010.

Depending on the jitter requirements, a band pass filter (BPF) is sometimes required between the CDC and the ADC. If the insertion loss of the BPF causes the clock amplitude to be too low for the ADC, or the clock source amplitude is too low to begin with, place an inexpensive amplifier between the CDC and the BPF.

Figure 6-8 represents a scenario where an LVCMOS single-ended clock output is used from a TI CDCM7005-SP with the clock signal path optimized for maximum amplitude and minimum jitter. This type of conditioning can be well-suited for use with greater than 150MHz of input frequency. The jitter of this setup is difficult to estimate and requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost amplifier because of insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter provided by the CDC is still not adequate. The total jitter at the CDCM7005-SP output depends largely on the phase noise of the VCXO selected, as well as the CDCM7005-SP, and typically has 50 to 100fs of RMS jitter. If the user determines that the jitter from the CDCM7005-SP with a VCXO is sufficient without further conditioning, clocking the ADS5474 directly from the CDCM7005-SP using differential LVPECL outputs is possible, as illustrated in Figure 6-9 (see the CDCM7005-SP 3.3V High Performance Clock Synchronizer and Jitter Cleaner data sheet for the exact schematic). This scenario can be an excellent choice for less than 150MHz of input frequency where jitter is not as critical. TI recommends carefully analyzing the required jitter before determining the proper approach.

Consult the CDCM7005 3.3V High Performance Clock Synchronizer and Jitter Cleaner data sheet for proper schematic and specifications regarding allowable input and output frequency and amplitude ranges.

Figure 6-8 Best Jitter Clock Circuit

Consult the CDCM7005 3.3V High Performance Clock Synchronizer and Jitter Cleaner data sheet for proper schematic and specifications regarding allowable input and output frequency and amplitude ranges.

Figure 6-9 Acceptable Jitter Clock Circuit