SLAS574B September   2013  – November 2025 ADS5474-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Input Configuration
      2. 6.1.2 Clock Inputs
      3. 6.1.3 Digital Outputs
  8. 7 Application and Implementation
    1. 7.1 Power Supply Recommendations
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Definition of Specifications
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

ADS5474-SP HFG Package, 84-Pin CFP (Top View) Figure 4-1 HFG Package, 84-Pin CFP (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AIN 17 I Differential input signal (positive)
AIN 18 I Differential input signal (negative)
AVDD3 37, 39, 41 P Analog power supply (3.3V)
AVDD5 4, 9, 14, 15, 20, 23, 25, 27, 29, 33 P Analog power supply (5V)
CLK 11 I Differential input clock (positive). Conversion is initiated on rising edge.
CLK 12 I Differential input clock (negative)
D0, D0 50, 51 O LVDS digital output pair, least-significant bit (LSB)
D1, D1,
D2–D5,
D6-D7,
D8-D12		 52, 53, 56–63, 65–68, 71–82 O LVDS digital output pairs
D13, D13 81, 82 O LVDS digital output pair, most significant bit (MSB)
DRY, DRY 84, 83 O Data ready LVDS output pair
DVDD3 2, 54, 70 P Digital and output driver power supply (3.3V)
GND 1,3, 8, 10, 13, 16, 19, 21, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 43, 55, 64, 69 GND Ground
NC 5, 6, 46, 47, 48, 49 N/A No connect
OVR, OVR 45, 44 O Over-range indicator LVDS output. A logic high signals an analog input in excess of the full-scale range.
PDWN 35 I Power-down (active high). Device is in sleep mode when PDWN pin is logic HIGH. ADC converter is awake when PDWN is logic LOW (grounded).
(This pin is not used on the ADS5463-SP and ADS5444-SP)
VCM 31 O Common-mode voltage output (3.1V nominal). Commonly used in DC-coupled applications to set the input signal to the correct common-mode voltage.
(This pin is not used on the ADS5463-SP and ADS5444-SP)
VREF 7 I/O Reference voltage input/output (2.4V nominal)
(1) I = input, O = output, GND = ground, P = power, I/O = bidirectional, N/A = not applicable