SLASF33A January   2024  – March 2025 TAC5412-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI
    9. 5.9  Switching Characteristics: SPI
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3  Input Channel Configuration
      4. 6.3.4  Reference Voltage
      5. 6.3.5  Microphone Bias
      6. 6.3.6  Digital PDM Microphone Record Channel
      7. 6.3.7  Signal-Chain Processing
        1. 6.3.7.1 ADC Signal-Chain
          1. 6.3.7.1.1  6 to 4 Input Select Multiplexer (6:4 MUX)
          2. 6.3.7.1.2  Programmable Channel Gain and Digital Volume Control
          3. 6.3.7.1.3  Programmable Channel Gain Calibration
          4. 6.3.7.1.4  Programmable Channel Phase Calibration
          5. 6.3.7.1.5  Programmable Digital High-Pass Filter
          6. 6.3.7.1.6  Programmable Digital Biquad Filters
          7. 6.3.7.1.7  Programmable Channel Summer and Digital Mixer
          8. 6.3.7.1.8  Configurable Digital Decimation Filters
            1. 6.3.7.1.8.1 Linear-phase filters
              1. 6.3.7.1.8.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.1.8.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.1.8.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.1.8.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.1.8.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.1.8.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.1.8.1.7 Sampling Rate: 192kHz or 176.4kHz
              8. 6.3.7.1.8.1.8 Sampling Rate: 384kHz or 352.8kHz
              9. 6.3.7.1.8.1.9 Sampling Rate: 768kHz or 705.6kHz
            2. 6.3.7.1.8.2 Low-latency Filters
              1. 6.3.7.1.8.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.8.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.8.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.8.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.8.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.1.8.3 Ultra-Low-Latency Filters
              1. 6.3.7.1.8.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.8.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.8.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.8.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.8.3.5 Sampling Rate: 192kHz or 176.4kHz
          9. 6.3.7.1.9  Automatic Gain Controller (AGC)
          10. 6.3.7.1.10 Voice Activity Detection (VAD)
          11. 6.3.7.1.11 Ultrasonic Activity Detection (UAD)
        2. 6.3.7.2 DAC Signal-Chain
          1. 6.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.2.2 Programmable Channel Gain Calibration
          3. 6.3.7.2.3 Programmable Digital High-Pass Filter
          4. 6.3.7.2.4 Programmable Digital Biquad Filters
          5. 6.3.7.2.5 Configurable Digital Interpolation Filters
            1. 6.3.7.2.5.1 Linear-phase filters
              1. 6.3.7.2.5.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.2.5.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.2.5.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.2.5.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.2.5.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.2.5.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.2.5.1.7 Sampling Rate: 192kHz or 176.4kHz
              8. 6.3.7.2.5.1.8 Sampling Rate: 384kHz or 352.8kHz
              9. 6.3.7.2.5.1.9 Sampling Rate 768kHz or 705.6kHz
            2. 6.3.7.2.5.2 Low-latency Filters
              1. 6.3.7.2.5.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.5.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.5.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.5.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.5.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.2.5.3 Ultra-Low-Latency Filters
              1. 6.3.7.2.5.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.5.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.5.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.5.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.5.3.5 Sampling Rate 192kHz or 176.4kHz
          6. 6.3.7.2.6 Programmable Digital Mixer
      8. 6.3.8  Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9  Input DC Fault Diagnostics
      10. 6.3.10 Power Tune Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Active Mode
      3. 6.4.3 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAC5412-Q1_B0_P0 Registers
      2. 7.1.2 TAC5412-Q1_B0_P1 Registers
      3. 7.1.3 TAC5412-Q1_B0_P3 Registers
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1  Programmable Coefficient Registers: Page 8
      2. 7.2.2  Programmable Coefficient Registers: Page 9
      3. 7.2.3  Programmable Coefficient Registers: Page 10
      4. 7.2.4  Programmable Coefficient Registers: Page 11
      5. 7.2.5  Programmable Coefficient Registers: Page 15
      6. 7.2.6  Programmable Coefficient Registers: Page 16
      7. 7.2.7  Programmable Coefficient Registers: Page 17
      8. 7.2.8  Programmable Coefficient Registers: Page 18
      9. 7.2.9  Programmable Coefficient Registers: Page 19
      10. 7.2.10 Programmable Coefficient Registers: Page 25
      11. 7.2.11 Programmable Coefficient Registers: Page 26
      12. 7.2.12 Programmable Coefficient Registers: Page 27
      13. 7.2.13 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Typical Characteristics
      5. 8.2.5 Example Device Register Configuration Script for EVM Setup
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.2.11 Programmable Coefficient Registers: Page 26

This register page shown in Table 7-228 consists of the programmable coefficients for the DAC brownout protection (BOP), thermal foldback (THF) protection and Limiter.

Table 7-226 Page 26 Programmable Coefficient Registers
ADDRESS REGISTER RESET DESCRIPTION
0x00 PAGE[7:0] 0x00 Device Page Register
0x14 BOP_ATTACK_COEFF_BYT1[7:0] 0x78 BOP Attack coefficient byte[31:24]
0x15 BOP_ATTACK_COEFF_BYT2[7:0] 0xD6 BOP Attack coefficient byte[23:16]
0x16 BOP_ATTACK_COEFF_BYTT3[7:0] 0xFC BOP Attack coefficient byte[15:8]
0x17 BOP_ATTACK_COEFF_BYTT4[7:0] 0x9F BOP Attack coefficient byte[7:0]
0x18 BOP_RELEASE_COEFF_BYT1[7:0] 0x40 BOP Release coefficient byte[31:24]
0x19 BOP_RELEASE_COEFF_BYT2[7:0] 0xBD BOP Release coefficient byte[23:16]
0x1A BOP_RELEASE_COEFF_BYTT3[7:0] 0xB7 BOP Release coefficient byte[15:8]
0x1B BOP_RELEASE_COEFF_BYTT4[7:0] 0xC0 BOP Release coefficient byte[7:0]
0x1C BOP_RESET_COUNTER_BYT1[7:0] 0x00 BOP Hold Count coefficient byte[31:24]
0x1D BOP_RESET_COUNTER_BYT2[7:0] 0x00 BOP Hold Count coefficient byte[23:16]
0x1E BOP_RESET_COUNTER_BYTT3[7:0] 0x09 BOP Hold Count coefficient byte[15:8]
0x1F BOP_RESET_COUNTER_BYTT4[7:0] 0x60 BOP Hold Count coefficient byte[7:0]
0x20 BOP_VSUP_TH1_BYT1[7:0] 0x00 BOP Supply Threshold1 coefficient byte[31:24]
0x21 BOP_VSUP_TH1_BYT2[7:0] 0x00 BOP Supply Threshold1 coefficient byte[23:16]
0x22 BOP_VSUP_TH1_BYTT3[7:0] 0x19 BOP Supply Threshold1 coefficient byte[15:8]
0x23 BOP_VSUP_TH1_BYTT4[7:0] 0x9A BOP Supply Threshold1 coefficient byte[7:0]
0x24 BOP_THRESHOLD1_BYT1[7:0] 0x2D BOP Threshold1 Gain coefficient byte[31:24]
0x25 BOP_THRESHOLD1_BYT2[7:0] 0x4E BOP Threshold1 Gain coefficient byte[23:16]
0x26 BOP_THRESHOLD1_BYTT3[7:0] 0xFB BOP Threshold1 Gain coefficient byte[15:8]
0x27 BOP_THRESHOLD1_BYTT4[7:0] 0xD6 BOP Threshold1 Gain coefficient byte[7:0]
0x28 BOP_VSUP_TH2_BYT1[7:0] 0x00 BOP Supply Threshold2 coefficient byte[31:24]
0x29 BOP_VSUP_TH2_BYT2[7:0] 0x00 BOP Supply Threshold2 coefficient byte[23:16]
0x2A BOP_VSUP_TH2_BYTT3[7:0] 0x16 BOP Supply Threshold2 coefficient byte[15:8]
0x2B BOP_VSUP_TH2_BYTT4[7:0] 0x66 BOP Supply Threshold2 coefficient byte[7:0]
0x2C BOP_THRESHOLD2_BYT1[7:0] 0x14 BOP Threshold2 Gain coefficient byte[31:24]
0x2D BOP_THRESHOLD2_BYT2[7:0] 0x3D BOP Threshold2 Gain coefficient byte[23:16]
0x2E BOP_THRESHOLD2_BYTT3[7:0] 0x13 BOP Threshold2 Gain coefficient byte[15:8]
0x2F BOP_THRESHOLD2_BYTT4[7:0] 0x62 BOP Threshold2 Gain coefficient byte[7:0]
0x30 THF_ATTACK_COEFF_BYT1[7:0] 0x78 THF Attack coefficient byte[31:24]
0x31 THF_ATTACK_COEFF_BYT2[7:0] 0xD6 THF Attack coefficient byte[23:16]
0x32 THF_ATTACK_COEFF_BYTT3[7:0] 0xFC THF Attack coefficient byte[15:8]
0x33 THF_ATTACK_COEFF_BYTT4[7:0] 0x9F THF Attack coefficient byte[7:0]
0x34 THF_RELEASE_COEFF_BYT1[7:0] 0x40 THF Release coefficient byte[31:24]
0x35 THF_RELEASE_COEFF_BYT2[7:0] 0xBD THF Release coefficient byte[23:16]
0x36 THF_RELEASE_COEFF_BYTT3[7:0] 0xB7 THF Release coefficient byte[15:8]
0x37 THF_RELEASE_COEFF_BYTT4[7:0] 0xC0 THF Release coefficient byte[7:0]
0x38 THF_RESET_COUNTER_BYT1[7:0] 0x00 THF Hold Count coefficient byte[31:24]
0x39 THF_RESET_COUNTER_BYT2[7:0] 0x00 THF Hold Count coefficient byte[23:16]
0x3A THF_RESET_COUNTER_BYTT3[7:0] 0x09 THF Hold Count coefficient byte[15:8]
0x3B THF_RESET_COUNTER_BYTT4[7:0] 0x60 THF Hold Count coefficient byte[7:0]
0x3C THF_TEMP_THRESHOLD_BYT1[7:0] 0x00 THF Temperature Threshold coefficient byte[31:24]
0x3D THF_TEMP_THRESHOLD_BYT2[7:0] 0x00 THF Temperature Threshold coefficient byte[23:16]
0x3E THF_TEMP_THRESHOLD_BYTT3[7:0] 0x23 THF Temperature Threshold coefficient byte[15:8]
0x3F THF_TEMP_THRESHOLD_BYTT4[7:0] 0x80 THF Temperature Threshold coefficient byte[7:0]
0x40 THF_MAX_ATTN_BYT1[7:0] 0x2D THF Max Attenuation coefficient byte[31:24]
0x41 THF_MAX_ATTN_BYT2[7:0] 0x6A THF Max Attenuation coefficient byte[23:16]
0x42 THF_MAX_ATTN_BYTT3[7:0] 0x86 THF Max Attenuation coefficient byte[15:8]
0x43 THF_MAX_ATTN_BYTT4[7:0] 0x6F THF Max Attenuation coefficient byte[7:0]
0x44 THF_SLOPE_BYT1[7:0] 0xFE THF Slope coefficient byte[31:24]
0x45 THF_SLOPE_BYT2[7:0] 0x66 THF Slope coefficient byte[23:16]
0x46 THF_SLOPE_BYTT3[7:0] 0x66 THF Slope coefficient byte[15:8]
0x47 THF_SLOPE_BYTT4[7:0] 0x66 THF Slope coefficient byte[7:0]
0x48 LIMITER_ATTACK_HYS_LEVEL_BYT1[7:0] 0x08 Distortion Limiter Attack Level Hysteresis coefficient byte[31:24]
0x49 LIMITER_ATTACK_HYS_LEVEL_BYT2[7:0] 0xF9 Distortion Limiter Attack Level Hysteresis coefficient byte[23:16]
0x4A LIMITER_ATTACK_HYS_LEVEL_BYTT3[7:0] 0xE4 Distortion Limiter Attack Level Hysteresis coefficient byte[15:8]
0x4B LIMITER_ATTACK_HYS_LEVEL_BYTT4[7:0] 0xD0 Distortion Limiter Attack Level Hysteresis coefficient byte[7:0]
0x4C LIMITER_RELEASE_HYS_LEVEL_BYT1[7:0] 0x07 Distortion Limiter Release Level Hysteresis coefficient byte[31:24]
0x4D LIMITER_RELEASE_HYS_LEVEL_BYT2[7:0] 0x21 Distortion Limiter Release Level Hysteresis coefficient byte[23:16]
0x4E LIMITER_RELEASE_HYS_LEVEL_BYTT3[7:0] 0x48 Distortion Limiter Release Level Hysteresis coefficient byte[15:8]
0x4F LIMITER_RELEASE_HYS_LEVEL_BYTT4[7:0] 0x2C Distortion Limiter Release Level Hysteresis coefficient byte[7:0]
0x50 BOP_LEVEL_HYS_SUP_BYT1[7:0] 0x00 BOP Level Hysteresis coefficient byte[31:24]
0x51 BOP_LEVEL_HYS_SUP_BYT2[7:0] 0x00 BOP Level Hysteresis coefficient byte[23:16]
0x52 BOP_LEVEL_HYS_SUP_BYTT3[7:0] 0x00 BOP Level Hysteresis coefficient byte[15:8]
0x53 BOP_LEVEL_HYS_SUP_BYTT4[7:0] 0x14 BOP Level Hysteresis coefficient byte[7:0]
0x54 BOP_LEVEL_HYS_GAIN_BYT1[7:0] 0x03 BOP gain Hysteresis coefficient byte[31:24]
0x55 BOP_LEVEL_HYS_GAIN_BYT2[7:0] 0xD7 BOP gain Hysteresis coefficient byte[23:16]
0x56 BOP_LEVEL_HYS_GAIN_BYTT3[7:0] 0x0A BOP gain Hysteresis coefficient byte[15:8]
0x57 BOP_LEVEL_HYS_GAIN_BYTT4[7:0] 0x3E BOP gain Hysteresis coefficient byte[7:0]
0x58 THF_GAIN_HYS_BYT1[7:0] 0x03 THF gain Hysteresis coefficient byte[31:24]
0x59 THF_GAIN_HYS_BYT2[7:0] 0xD7 THF gain Hysteresis coefficient byte[23:16]
0x5A THF_GAIN_HYS_BYTT3[7:0] 0x0A THF gain Hysteresis coefficient byte[15:8]
0x5B THF_GAIN_HYS_BYTT4[7:0] 0x3D THF gain Hysteresis coefficient byte[7:0]