SLASF33A January   2024  – March 2025 TAC5412-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI
    9. 5.9  Switching Characteristics: SPI
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3  Input Channel Configuration
      4. 6.3.4  Reference Voltage
      5. 6.3.5  Microphone Bias
      6. 6.3.6  Digital PDM Microphone Record Channel
      7. 6.3.7  Signal-Chain Processing
        1. 6.3.7.1 ADC Signal-Chain
          1. 6.3.7.1.1  6 to 4 Input Select Multiplexer (6:4 MUX)
          2. 6.3.7.1.2  Programmable Channel Gain and Digital Volume Control
          3. 6.3.7.1.3  Programmable Channel Gain Calibration
          4. 6.3.7.1.4  Programmable Channel Phase Calibration
          5. 6.3.7.1.5  Programmable Digital High-Pass Filter
          6. 6.3.7.1.6  Programmable Digital Biquad Filters
          7. 6.3.7.1.7  Programmable Channel Summer and Digital Mixer
          8. 6.3.7.1.8  Configurable Digital Decimation Filters
            1. 6.3.7.1.8.1 Linear-phase filters
              1. 6.3.7.1.8.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.1.8.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.1.8.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.1.8.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.1.8.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.1.8.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.1.8.1.7 Sampling Rate: 192kHz or 176.4kHz
              8. 6.3.7.1.8.1.8 Sampling Rate: 384kHz or 352.8kHz
              9. 6.3.7.1.8.1.9 Sampling Rate: 768kHz or 705.6kHz
            2. 6.3.7.1.8.2 Low-latency Filters
              1. 6.3.7.1.8.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.8.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.8.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.8.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.8.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.1.8.3 Ultra-Low-Latency Filters
              1. 6.3.7.1.8.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.8.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.8.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.8.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.8.3.5 Sampling Rate: 192kHz or 176.4kHz
          9. 6.3.7.1.9  Automatic Gain Controller (AGC)
          10. 6.3.7.1.10 Voice Activity Detection (VAD)
          11. 6.3.7.1.11 Ultrasonic Activity Detection (UAD)
        2. 6.3.7.2 DAC Signal-Chain
          1. 6.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.2.2 Programmable Channel Gain Calibration
          3. 6.3.7.2.3 Programmable Digital High-Pass Filter
          4. 6.3.7.2.4 Programmable Digital Biquad Filters
          5. 6.3.7.2.5 Configurable Digital Interpolation Filters
            1. 6.3.7.2.5.1 Linear-phase filters
              1. 6.3.7.2.5.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.2.5.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.2.5.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.2.5.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.2.5.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.2.5.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.2.5.1.7 Sampling Rate: 192kHz or 176.4kHz
              8. 6.3.7.2.5.1.8 Sampling Rate: 384kHz or 352.8kHz
              9. 6.3.7.2.5.1.9 Sampling Rate 768kHz or 705.6kHz
            2. 6.3.7.2.5.2 Low-latency Filters
              1. 6.3.7.2.5.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.5.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.5.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.5.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.5.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.2.5.3 Ultra-Low-Latency Filters
              1. 6.3.7.2.5.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.5.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.5.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.5.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.5.3.5 Sampling Rate 192kHz or 176.4kHz
          6. 6.3.7.2.6 Programmable Digital Mixer
      8. 6.3.8  Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9  Input DC Fault Diagnostics
      10. 6.3.10 Power Tune Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Active Mode
      3. 6.4.3 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAC5412-Q1_B0_P0 Registers
      2. 7.1.2 TAC5412-Q1_B0_P1 Registers
      3. 7.1.3 TAC5412-Q1_B0_P3 Registers
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1  Programmable Coefficient Registers: Page 8
      2. 7.2.2  Programmable Coefficient Registers: Page 9
      3. 7.2.3  Programmable Coefficient Registers: Page 10
      4. 7.2.4  Programmable Coefficient Registers: Page 11
      5. 7.2.5  Programmable Coefficient Registers: Page 15
      6. 7.2.6  Programmable Coefficient Registers: Page 16
      7. 7.2.7  Programmable Coefficient Registers: Page 17
      8. 7.2.8  Programmable Coefficient Registers: Page 18
      9. 7.2.9  Programmable Coefficient Registers: Page 19
      10. 7.2.10 Programmable Coefficient Registers: Page 25
      11. 7.2.11 Programmable Coefficient Registers: Page 26
      12. 7.2.12 Programmable Coefficient Registers: Page 27
      13. 7.2.13 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Typical Characteristics
      5. 8.2.5 Example Device Register Configuration Script for EVM Setup
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.1.2 TAC5412-Q1_B0_P1 Registers

Table 7-105 lists the memory-mapped registers for the TAC5412-Q1_B0_P1 registers. All register offset addresses not listed in Table 7-105 are considered as reserved locations and the register contents are not to be modified.

Table 7-105 TAC5412-Q1_B0_P1 Registers
AddressAcronymRegister NameReset ValueSection
0x0PAGE_CFGDevice page register0x00Section 7.1.2.1
0x3DSP_CFG0DSP configuration register 00x00Section 7.1.2.2
0xDCLK_CFG0Clock configuration register 00x00Section 7.1.2.3
0xECHANNEL_CFG1ADC channel configuration register0x00Section 7.1.2.4
0x17SRC_CFG0SRC configuration register 10x00Section 7.1.2.5
0x18SRC_CFG1SRC configuration register 20x00Section 7.1.2.6
0x1ELPAD_CFG1Low power activity detection configuration register0x20Section 7.1.2.7
0x20LPAD_LPSG_CFG1Low power activity detection and Low power signal generation common configuration register 10x00Section 7.1.2.8
0x24AGC_CFGAGC configuration register 20x00Section 7.1.2.9
0x2CMIXER_CFG0MIXER configuration register 00x00Section 7.1.2.10
0x2FINT_MASK0Interrupt mask register 00xFFSection 7.1.2.11
0x30INT_MASK1Interrupt mask register 10x0FSection 7.1.2.12
0x31INT_MASK2Interrupt mask register 20x00Section 7.1.2.13
0x32INT_MASK4Interrupt mask register 40x00Section 7.1.2.14
0x33INT_MASK5Interrupt mask register 50x30Section 7.1.2.15
0x34INT_LTCH0Latched interrupt readback register 00x00Section 7.1.2.16
0x35CHx_LTCHLatched summary of diagnostics register0x00Section 7.1.2.17
0x36IN_CH1_LTCHChannel 1 input DC faults diagnostics latched status register0x00Section 7.1.2.18
0x37IN_CH2_LTCHChannel 2 input DC faults diagnostics latched status register0x00Section 7.1.2.19
0x38ADC_CHx_OVRLDADC overload fault detection mask0x00Section 7.1.2.20
0x39OUT_CH2_LTCHChannel 2 output DC faults diagnostics latched status register0x00Section 7.1.2.21
0x3AINT_LTCH1Latched interrupt readback register 10x00Section 7.1.2.22
0x3BINT_LTCH2Latched interrupt readback register 20x00Section 7.1.2.23
0x3CINT_LIVE0Live Interrupt readback register 00x00Section 7.1.2.24
0x3DCHx_LIVELive summary of diagnostics registers0x00Section 7.1.2.25
0x3EIN_CH1_LIVEChannel 1 input DC faults diagnostics live status register0x00Section 7.1.2.26
0x3FIN_CH2_LIVEChannel 2 input DC faults diagnostics live status register0x00Section 7.1.2.27
0x42INT_LIVE1Live interrupt readback register 10x00Section 7.1.2.28
0x43INT_LIVE2Live interrupt readback register 20x00Section 7.1.2.29
0x46DIAG_CFG0Input diagnostics configuration register 00x00Section 7.1.2.30
0x47DIAG_CFG1Input diagnostics configuration register 10x37Section 7.1.2.31
0x48DIAG_CFG2Input diagnostics configuration register 20x87Section 7.1.2.32
0x4ADIAG_CFG4Input diagnostics configuration register 40xB8Section 7.1.2.33
0x4BDIAG_CFG5Input diagnostics configuration register 50x00Section 7.1.2.34
0x4CDIAG_CFG6Input diagnostics configuration register 60xA2Section 7.1.2.35
0x4DDIAG_CFG7Input diagnostics configuration register 70x48Section 7.1.2.36
0x4EDIAG_CFG8Input diagnostics configuration register 80xBASection 7.1.2.37
0x4FDIAG_CFG9Input diagnostics configuration register 90x4BSection 7.1.2.38
0x50DIAG_CFG10Input diagnostics configuration register 100x88Section 7.1.2.39
0x51DIAG_CFG11Input diagnostics configuration register 110x40Section 7.1.2.40
0x52DIAG_CFG12Input diagnostics configuration register 120x44Section 7.1.2.41
0x53DIAG_CFG13Input diagnostics configuration register 130x00Section 7.1.2.42
0x54DIAG_CFG14Input diagnostics configuration register 140x48Section 7.1.2.43
0x55DIAGDATA_CFGInput diagnostics data configuration register0x00Section 7.1.2.44
0x56DIAG_MON_MSB_VBATDiagnostics SAR VBATIN monitor data MSB byte0x00Section 7.1.2.45
0x57DIAG_MON_LSB_VBATDiagnostics SAR VBATIN monitor data LSB nibble0x00Section 7.1.2.46
0x58DIAG_MON_MSB_MBIASDiagnostics SAR MICBIAS monitor data MSB byte0x00Section 7.1.2.47
0x59DIAG_MON_LSB_MBIASDiagnostics SAR MICBIAS monitor data LSB nibble0x01Section 7.1.2.48
0x5ADIAG_MON_MSB_IN1PDiagnostics SAR IN1P monitor data MSB byte0x00Section 7.1.2.49
0x5BDIAG_MON_LSB_IN1PDiagnostics SAR IN1P monitor data LSB nibble0x02Section 7.1.2.50
0x5CDIAG_MON_MSB_IN1MDiagnostics SAR IN1M monitor data MSB byte0x00Section 7.1.2.51
0x5DDIAG_MON_LSB_IN1MDiagnostics SAR IN1M monitor data LSB nibble0x03Section 7.1.2.52
0x5EDIAG_MON_MSB_IN2PDiagnostics SAR IN2P monitor data MSB byte0x00Section 7.1.2.53
0x5FDIAG_MON_LSB_IN2PDiagnostics SAR IN2P monitor data LSB nibble0x04Section 7.1.2.54
0x60DIAG_MON_MSB_IN2MDiagnostics SAR IN2M monitor data MSB byte0x00Section 7.1.2.55
0x61DIAG_MON_LSB_IN2MDiagnostics SAR IN2M monitor data LSB nibble0x05Section 7.1.2.56
0x6ADIAG_MON_MSB_TEMPDiagnostics SAR Temperature monitor data MSB byte0x00Section 7.1.2.57
0x6BDIAG_MON_LSB_TEMPDiagnostics SAR Temperature monitor data LSB nibble0x0ASection 7.1.2.58
0x6CDIAG_MON_MSB_MBIAS_LOADDiagnostics SAR MICBIAS LOAD Current monitor data MSB byte0x00Section 7.1.2.59
0x6DDIAG_MON_LSB_MBIAS_LOADDiagnostics SAR MICBIAS LOAD Current monitor data LSB nibble0x0BSection 7.1.2.60
0x6EDIAG_MON_MSB_AVDDDiagnostics SAR AVDD monitor data MSB byte0x00Section 7.1.2.61
0x6FDIAG_MON_LSB_AVDDDiagnostics SAR AVDD monitor data LSB nibble0x0CSection 7.1.2.62
0x70DIAG_MON_MSB_GPADiagnostics SAR GPA monitor data MSB byte0x00Section 7.1.2.63
0x71DIAG_MON_LSB_GPADiagnostics SAR GPA monitor data LSB nibble register0x0DSection 7.1.2.64
0x72BOOST_CFGBoost configuration register0x00Section 7.1.2.65
0x73MICBIAS_CFGMicbias configuration register0xA0Section 7.1.2.66

7.1.2.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x00]

PAGE_CFG is shown in Table 7-106.

Return to the Summary Table.

The device memory map is divided into pages. This register sets the page.

Table 7-106 PAGE_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-0PAGE[7:0]R/W00000000bThese bits set the device page.
0d = Page 0
1d = Page 1
2d to 254d = Page 2 to page 254 respectively
255d = Page 255

7.1.2.2 DSP_CFG0 Register (Address = 0x3) [Reset = 0x00]

DSP_CFG0 is shown in Table 7-107.

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This register is the configuration register for on-the-fly filter updates.

Table 7-107 DSP_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6RESERVEDR0bReserved bit; Write only reset value
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0EN_BQ_OTF_CHGR/W0bEnable run-time changes to Biquad settings.
0d = Disable on the fly biquad changes
1d = Enable on the fly biquad changes

7.1.2.3 CLK_CFG0 Register (Address = 0xD) [Reset = 0x00]

CLK_CFG0 is shown in Table 7-108.

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This register is the Clock configuration register 0.

Table 7-108 CLK_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7CNT_TGT_CFG_OVR_PASIR/W0bASI controller target Config Override Register
0d = controller-target Config as per PASI_CNT_CFG bit.
1d = Override the standard behavior of the PASI_CNT_CFG. In this case the clock auto detect feature is not available.
PASI_CNT_CFG = 0 : BCLK is input but FSYNC is output.
PASI_CNT_CFG = 1 : BCLK is output but FSYNC in input.
6CNT_TGT_CFG_OVR_SASIR/W0bASI controller target Config Override Register
0d = controller-target Config as per SASI_CNT_CFG bit.
1d = Override the standard behavior of the SASI_CNT_CFG. In this case the clock auto detect feature is not available.
SASI_CNT_CFG = 0 : BCLK is input but FSYNC is output.
SASI_CNT_CFG = 1 : BCLK is output but FSYNC in input.
5-3RESERVEDR0bReserved bits; Write only reset value
2PASI_USE_INT_FSYNCR/W0bFor Primary use internal FSYNC in controller mode configuration.
0d = Use external FSYNC
1d = Use internal FSYNC
1SASI_USE_INT_FSYNCR/W0bFor Secondary use internal FSYNC in controller mode configuration.
0d = Use external FSYNC
1d = Use internal FSYNC
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.4 CHANNEL_CFG1 Register (Address = 0xE) [Reset = 0x00]

CHANNEL_CFG1 is shown in Table 7-109.

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This is the ADC channel dynamic power-on or off configuration register.

Table 7-109 CHANNEL_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7FORCE_DYN_MODE_CUST_MAX_CHR/W0bADC Force dynamic mode custom max channel
0d = In Dynamic, Max channel is based on ADC_DYN_MAXCH_SEL
1d = In Dynamic mode, max channel is custom as DYN_MODE_CUST_MAX_CH
6-3DYN_MODE_CUST_MAX_CH[3:0]R/W0000bADC Dynamic mode custom max channel configuration
[3]->CH4_EN
[2]->CH3_EN
[1]->CH2_EN
[0]->CH1_EN
2-0RESERVEDR0bReserved bits; Write only reset values

7.1.2.5 SRC_CFG0 Register (Address = 0x17) [Reset = 0x00]

SRC_CFG0 is shown in Table 7-110.

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This register is configuration register 1 for SRC.

Table 7-110 SRC_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7SRC_ENR/W0bSRC enable config
0b = SRC disable
1b = SRC enable
6DIS_AUTO_SRC_DETR/W0bSRC auto detect config
0b = SRC auto detect enabled
1b = SRC auto detect disabled
5-0RESERVEDR0bReserved bits; Write only reset value

7.1.2.6 SRC_CFG1 Register (Address = 0x18) [Reset = 0x00]

SRC_CFG1 is shown in Table 7-111.

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This register is configuration register 2 for SRC.

Table 7-111 SRC_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7MAIN_FS_CUSTOM_CFGR/W0bMain Fs custom config
0b = Main Fs is auto inferred
1b = Main Fs need to be selected from MAIN_FS_SELECT_CFG
6MAIN_FS_SELECT_CFGR/W0bMain Fs select config
0b = PASI Fs shall be used as Main Fs
1b = SASI Fs shall be used as Main Fs
5-3MAIN_AUX_RATIO_M_CUSTOM_CFG[2:0]R/W000bMain and Aux Fs Ratio m:n config
0d = m is auto inferred
1d = 1
2d = 2
3d = 3
4d = 4
5d = Reserved
6d = 6
7d = Reserved
2-0MAIN_AUX_RATIO_N_CUSTOM_CFG[2:0]R/W000bMain and Aux Fs Ratio m:n config
0d = n is auto inferred
1d = 1
2d = 2
3d = 3
4d = 4
5d = Reserved
6d = 6
7d = Reserved

7.1.2.7 LPAD_CFG1 Register (Address = 0x1E) [Reset = 0x20]

LPAD_CFG1 is shown in Table 7-112.

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This register is the voice activity detection or ultrasonic activity detection configuration register 1.

Table 7-112 LPAD_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6LPAD_MODE[1:0]R/W00bAuto ADC power up / power down configuration selection.
0d = User initiated ADC power-up and ADC power-down
1d = VAD/UAD interrupt based ADC power up and ADC power down
2d = VAD/UAD interrupt based ADC power up but user initiated ADC power down
3d = Reserved
5-4LPAD_CH_SEL[1:0]R/W10bVAD channel select.
0d = Channel 1 is monitored for VAD/UAD activity
1d = Channel 2 is monitored for VAD/UAD activity
2d = Channel 3 is monitored for VAD/UAD activity
3d = Channel 4 is monitored for VAD/UAD activity
3LPAD_DOUT_INT_CFGR/W0bDOUT interrupt configuration.
0d = DOUT pin is not enabled for interrupt function
1d = DOUT pin is enabled to support interrupt output when channel data in not being recorded
2RESERVEDR0bReserved bit; Write only reset value
1LPAD_PD_DET_ENR/W0bEnable ASI output data during VAD/UAD activity.
0d = VAD/UAD processing is not enabled during ADC recording
1d = VAD/UAD processing is enabled during ADC recording and VAD interrupts are generated as configured
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.8 LPAD_LPSG_CFG1 Register (Address = 0x20) [Reset = 0x00]

LPAD_LPSG_CFG1 is shown in Table 7-113.

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This register is configuration register 1 for VAD/UAD/UAG.

Table 7-113 LPAD_LPSG_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6LPAD_LPSG_CLK_CFG[1:0]R/W00bClock select for VAD/UAD/UAG
0d = VAD/UAD/UAG processing using internal oscillator clock
1d = VAD/UAD/UAG processing using external clock on BCLK input
2d = VAD/UAD/UAG processing using external clock on CCLK input
3d = Custom clock configuration based on CNT_CFG, CLK_SRC and CLKGEN_CFG registers in page 0
5-4LPAD_LPSG_EXT_CLK_CFG[1:0]R/W00bClock configuration using external clock for VAD/UAD/UAG
0d = External clock is 24.576 MHz
1d = External clock is 6.144 MHz (Not Supported)
2d = External clock is 12.288 MHz
3d = External clock is 18.432 MHz
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1-0RESERVEDR0bReserved bits; Write only reset values

7.1.2.9 AGC_CFG Register (Address = 0x24) [Reset = 0x00]

AGC_CFG is shown in Table 7-114.

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This register is configuration register 2 for AGC.

Table 7-114 AGC_CFG Register Field Descriptions
BitFieldTypeResetDescription
7AGC_CH1_ENR/W0bAGC Channel 1 enable config
0d = disable
1d = enable
6AGC_CH2_ENR/W0bAGC Channel 2 enable config
0d = disable
1d = enable
5AGC_CH3_ENR/W0bAGC Channel 3 enable config
0d = disable
1d = enable
4AGC_CH4_ENR/W0bAGC Channel 4 enable config
0d = disable
1d = enable
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.10 MIXER_CFG0 Register (Address = 0x2C) [Reset = 0x00]

MIXER_CFG0 is shown in Table 7-115.

Return to the Summary Table.

This register is the MIXER configuration register 0.

Table 7-115 MIXER_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6EN_SIDE_CHAIN_MIXERR/W0bEnable Side Chain Mixer
0b = Disabled
1b = Enabled
5EN_ADC_CHANNEL_MIXERR/W0bEnable ADC Channel Mixer
0b = Disabled
1b = Enabled
4EN_LOOPBACK_MIXERR/W0bEnable Loopback Mixer
0b = Disabled
1b = Enabled
3-0RESERVEDR0bReserved bits; Write only reset value

7.1.2.11 INT_MASK0 Register (Address = 0x2F) [Reset = 0xFF]

INT_MASK0 is shown in Table 7-116.

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This register is the interrupt mask register 0.

Table 7-116 INT_MASK0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_MASK0R/W1bClock error interrupt mask.
0b = Don't Mask
1b = Mask
6INT_MASK0R/W1bPLL Lock interrupt mask.
0b = Don't Mask
1b = Mask
5INT_MASK0R/W1bBoost Over Temperature interrupt mask.
0b = Don't Mask
1b = Mask
4INT_MASK0R/W1bBoost Over Current interrupt mask.
0b = Don't Mask
1b = Mask
3INT_MASK0R/W1bBoost MO interrupt mask.
0b = Don't Mask
1b = Mask
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.12 INT_MASK1 Register (Address = 0x30) [Reset = 0x0F]

INT_MASK1 is shown in Table 7-117.

Return to the Summary Table.

This register is the interrupt mask register 1.

Table 7-117 INT_MASK1 Register Field Descriptions
BitFieldTypeResetDescription
7INT_MASK1R/W0bChannel-1(INP1/INM1) Input DC Faults Diagnostic Interrupt Mask.
0b = Don't Mask
1b = Mask
6INT_MASK1R/W0bChannel-2(INP2/INM2) Input DC Faults Diagnostic Interrupt Mask.
0b = Don't Mask
1b = Mask
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3INT_MASK1R/W1bInput Faults Diagnostic Interrupt Mask for "Short to VBATIN" detect when VBATIN Voltage is less than MICBIAS Voltage.
0b = Don't Mask
1b = Mask
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.13 INT_MASK2 Register (Address = 0x31) [Reset = 0x00]

INT_MASK2 is shown in Table 7-118.

Return to the Summary Table.

This register is the interrupt mask register 2.

Table 7-118 INT_MASK2 Register Field Descriptions
BitFieldTypeResetDescription
7INT_MASK2R/W0bInput Diagnostics - Open Inputs Fault Interrupt Mask.
0b = Don't Mask
1b = Mask
6INT_MASK2R/W0bInput Diagnostics - Inputs Shorted Fault Interrupt Mask.
0b = Don't Mask
1b = Mask
5INT_MASK2R/W0bInput Diagnostics - INP Shorted to GND Fault Interrupt Mask.
0b = Don't Mask
1b = Mask
4INT_MASK2R/W0bInput Diagnostics - INM Shorted to GND Fault Interrupt Mask.
0b = Don't Mask
1b = Mask
3INT_MASK2R/W0bInput Diagnostics - INP Shorted to MICBIAS Fault Interrupt Mask.
0b = Don't Mask
1b = Mask
2INT_MASK2R/W0bInput Diagnostics - INM Shorted to MICBIAS Fault Interrupt Mask.
0b = Don't Mask
1b = Mask
1INT_MASK2R/W0bInput Diagnostics - INP Shorted to VBATIN Fault Interrupt Mask.
0b = Don't Mask
1b = Mask
0INT_MASK2R/W0bInput Diagnostics - INM Shorted to VBATIN Fault Interrupt Mask.
0b = Don't Mask
1b = Mask

7.1.2.14 INT_MASK4 Register (Address = 0x32) [Reset = 0x00]

INT_MASK4 is shown in Table 7-119.

Return to the Summary Table.

This register is the interrupt mask register 4.

Table 7-119 INT_MASK4 Register Field Descriptions
BitFieldTypeResetDescription
7INT_MASK4R/W0bINP overvoltage fault mask.
0b = Don't Mask
1b = Mask
6INT_MASK4R/W0bINM overvoltage fault mask.
0b = Don't Mask
1b = Mask
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.15 INT_MASK5 Register (Address = 0x33) [Reset = 0x30]

INT_MASK5 is shown in Table 7-120.

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This register is the interrupt mask register 5.

Table 7-120 INT_MASK5 Register Field Descriptions
BitFieldTypeResetDescription
7INT_MASK5R/W0bGPA up threshold fault mask.
0b = Don't Mask
1b = Mask
6INT_MASK5R/W0bGPA low threshold fault mask.
0b = Don't Mask
1b = Mask
5INT_MASK5R/W1bVAD power up detect interrupt mask.
0b = Don't Mask
1b = Mask
4INT_MASK5R/W1bVAD power down detect interrupt mask.
0b = Don't Mask
1b = Mask
3INT_MASK5R/W0bMicbias short circuit fault mask.
0b = Don't Mask
1b = Mask
2INT_MASK5R/W0bMicbias High current fault mask.
0b = Don't Mask
1b = Mask
1INT_MASK5R/W0bMicbias Low current fault mask.
0b = Don't Mask
1b = Mask
0INT_MASK5R/W0bMicbias Over voltage fault mask.
0b = Don't Mask
1b = Mask

7.1.2.16 INT_LTCH0 Register (Address = 0x34) [Reset = 0x00]

INT_LTCH0 is shown in Table 7-121.

Return to the Summary Table.

This register is the latched interrupt readback register 0.

Table 7-121 INT_LTCH0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LTCH0R0bInterrupt due to clock error (self clearing bit).
0b = No interrupt
1b = Interrupt
6INT_LTCH0R0bInterrupt due to PLL Lock (self clearing bit)
0b = No interrupt
1b = Interrupt
5INT_LTCH0R0bInterrupt due to Boost Over Temperature (self clearing bit).
0b = No interrupt
1b = Interrupt
4INT_LTCH0R0bInterrupt due to Boost Over Current.(self clearing bit).
0b = No interrupt
1b = Interrupt
3INT_LTCH0R0bInterrupt due to Boost MO. (self clearing bit).
0b = No interrupt
1b = Interrupt
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.17 CHx_LTCH Register (Address = 0x35) [Reset = 0x00]

CHx_LTCH is shown in Table 7-122.

Return to the Summary Table.

This register is the channel level diagnostics latched status register.

Table 7-122 CHx_LTCH Register Field Descriptions
BitFieldTypeResetDescription
7STS_CHx_LTCHR0bStatus of Input CH1_LTCH (INP1/INM1).
0b = No faults occurred in input channel 1
1b = Fault or Faults have occurred in input channel 1
6STS_CHx_LTCHR0bStatus of Input CH2_LTCH (INP2/INM2).
0b = No faults occurred in input channel 2
1b = Fault or Faults have occurred in input channel 2
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3STS_CHx_LTCHR0bStatus on fault due "Short to VBATIN fault detected when VBATIN is less than MICBIAS"
0b = Short to VBATIN fault when VBATIN is less than MICBIAS did NOT occur in any channel
1b = Short to VBATIN fault when VBATIN is less than MICBIAS has occurred in at least one channel
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.18 IN_CH1_LTCH Register (Address = 0x36) [Reset = 0x00]

IN_CH1_LTCH is shown in Table 7-123.

Return to the Summary Table.

This register is the latched status register for channel 1 input DC faults diagnostics.

Table 7-123 IN_CH1_LTCH Register Field Descriptions
BitFieldTypeResetDescription
7IN_CH1_LTCHR0bInput Channel-1(INP1/INM1) Open Inputs (self clearing bit).
0b = No Open Inputs
1b = Open Inputs
6IN_CH1_LTCHR0bInput Channel-1(INP1/INM1) Inputs Shorted (self clearing bit).
0b = No Input Shorted
1b = Input Shorted each Other
5IN_CH1_LTCHR0bInput Channel-1 INP Shorted to GND (self clearing bit).
0b = INP not shorted to GND
1b = INP shorted to GND
4IN_CH1_LTCHR0bInput Channel-1 INM1 Shorted to GND (self clearing bit).
0b = INM not shorted to GND
1b = INM shorted to GND
3IN_CH1_LTCHR0bInput Channel-1 INP1 Shorted to MICBIAS (self clearing bit).
0b = INP not shorted to MICBIAS
1b = INP shorted to MICBIAS
2IN_CH1_LTCHR0bInput Channel-1 INM1 Shorted to MICBIAS (self clearing bit).
0b = INM not shorted to MICBIAS
1b = INM shorted to MICBIAS
1IN_CH1_LTCHR0bInput Channel-1 INP1 Shorted to VBATIN (self clearing bit).
0b = INP not shorted to VBATIN
1b = INP shorted to VBATIN
0IN_CH1_LTCHR0bInput Channel-1 INM1 Shorted to VBATIN (self clearing bit).
0b = INM not shorted to VBATIN
1b = INM shorted to VBATIN

7.1.2.19 IN_CH2_LTCH Register (Address = 0x37) [Reset = 0x00]

IN_CH2_LTCH is shown in Table 7-124.

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This register is the latched status register for channel 2 input DC faults diagnostics.

Table 7-124 IN_CH2_LTCH Register Field Descriptions
BitFieldTypeResetDescription
7IN_CH2_LTCHR0bInput Channel-2(INP2/INM2) Open Inputs (self clearing bit).
0b = No Open Inputs
1b = Open Inputs
6IN_CH2_LTCHR0bInput Channel-2(INP2/INM2) Inputs Shorted (self clearing bit).
0b = No Input Shorted
1b = Input Shorted each Other
5IN_CH2_LTCHR0bInput Channel-2 INP2 Shorted to GND (self clearing bit).
0b = INP not shorted to GND
1b = INP shorted to GND
4IN_CH2_LTCHR0bInput Channel-2 INM2 Shorted to GND (self clearing bit).
0b = INM not shorted to GND
1b = INM shorted to GND
3IN_CH2_LTCHR0bInput Channel-2 INP2 Shorted to MICBIAS (self clearing bit).
0b = INP not shorted to MICBIAS
1b = INP shorted to MICBIAS
2IN_CH2_LTCHR0bInput Channel-2 INM2 Shorted to MICBIAS (self clearing bit).
0b = INM not shorted to MICBIAS
1b = INM shorted to MICBIAS
1IN_CH2_LTCHR0bInput Channel-2 INP2 Shorted to VBATIN (self clearing bit).
0b = INP not shorted to VBATIN
1b = INP shorted to VBATIN
0IN_CH2_LTCHR0bInput Channel-2 INM2 Shorted to VBATIN (self clearing bit).
0b = INM not shorted to VBATIN
1b = INM shorted to VBATIN

7.1.2.20 ADC_CHx_OVRLD Register (Address = 0x38) [Reset = 0x00]

ADC_CHx_OVRLD is shown in Table 7-125.

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This register is the ADC overload fault detection mask register.

Table 7-125 ADC_CHx_OVRLD Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6RESERVEDR0bReserved bit; Write only reset value
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3MASK_ADC_CH1_OVRLD_FLAGR/W0bADC CH1 OVRLD fault mask.
0b = Don't Mask
1b = Mask
2MASK_ADC_CH2_OVRLD_FLAGR/W0bADC CH2 OVRLD fault mask.
0b = Don't Mask
1b = Mask
1-0RESERVEDR0bReserved bits; Write only reset value

7.1.2.21 OUT_CH2_LTCH Register (Address = 0x39) [Reset = 0x00]

OUT_CH2_LTCH is shown in Table 7-126.

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This register is the latched status register for channel 2 output DC faults diagnostics.

Table 7-126 OUT_CH2_LTCH Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6RESERVEDR0bReserved bit; Write only reset value
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3-2RESERVEDR0bReserved bits; Write only reset value
1MASK_AREG_SC_FLAGR/W0bAREG SC fault mask.
0b = Don't Mask
1b = Mask
0AREG_SC_FLAG_LTCHR0bAREG SC fault (self clearing bit).
0b = No AREG short circuit fault
1b = AREG short circuit fault

7.1.2.22 INT_LTCH1 Register (Address = 0x3A) [Reset = 0x00]

INT_LTCH1 is shown in Table 7-127.

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This is the register 1 for latched interrupt readback.

Table 7-127 INT_LTCH1 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LTCH1R0bChannel-1 INP1 Over Voltage (self clearing bit).
0b = No INP Over Voltage fault
1b = INP Over Voltage fault has occurred
6INT_LTCH1R0bChannel-1 INM1 Over Voltage (self clearing bit).
0b = No INM Over Voltage fault
1b = INM Over Voltage fault has occurred
5INT_LTCH1R0bChannel-2 INP2 Over Voltage (self clearing bit).
0b = No INP Over Voltage fault
1b = INP Over Voltage fault has occurred
4INT_LTCH1R0bChannel-2 INM2 Over Voltage (self clearing bit).
0b = No INM Over Voltage fault
1b = INM Over Voltage fault has occurred
3INT_LTCH1R0bInterrupt due to Headset Insert Detection (self clearing bit).
0b = No interrupt
1b = Interrupt
2INT_LTCH1R0bInterrupt due to Headset Remove Detection (self clearing bit).
0b = No interrupt
1b = Interrupt
1INT_LTCH1R0bInterrupt due to Headset hook(button) (self clearing bit).
0b = No interrupt
1b = Interrupt
0INT_LTCH1R0bInterrupt due to MIPS overload (self clearing bit)
0b = No interrupt
1b = Interrupt

7.1.2.23 INT_LTCH2 Register (Address = 0x3B) [Reset = 0x00]

INT_LTCH2 is shown in Table 7-128.

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This is the register 2 for latched interrupt readback.

Table 7-128 INT_LTCH2 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LTCH2R0bInterrupt due to GPA up threshold fault (self clearing bit).
0b = No interrupt
1b = Interrupt
6INT_LTCH2R0bInterrupt due to GPA low threshold fault (self clearing bit)
0b = No interrupt
1b = Interrupt
5INT_LTCH2R0bInterrupt due to VAD power up detect (self clearing bit).
0b = No interrupt
1b = Interrupt
4INT_LTCH2R0bInterrupt due to VAD power down detect (self clearing bit).
0b = No interrupt
1b = Interrupt
3INT_LTCH2R0bInterrupt due to Micbias short circuit condition (self clearing bit)
0b = No interrupt
1b = Interrupt
2INT_LTCH2R0bInterrupt due to Micbias High current fault (self clearing bit).
0b = No interrupt
1b = Interrupt
1INT_LTCH2R0bInterrupt due to Micbias Low current fault (self clearing bit)
0b = No interrupt
1b = Interrupt
0INT_LTCH2R0bInterrupt due to Micbias Over voltage fault (self clearing bit).
0b = No interrupt
1b = Interrupt

7.1.2.24 INT_LIVE0 Register (Address = 0x3C) [Reset = 0x00]

INT_LIVE0 is shown in Table 7-129.

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This is the register 0 for live interrupt readback.

Table 7-129 INT_LIVE0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LIVE0R0bInterrupt due to clock error .
0b = No interrupt
1b = Interrupt
6INT_LIVE0R0bInterrupt due to PLL Lock
0b = No interrupt
1b = Interrupt
5INT_LIVE0R0bInterrupt due to Boost Over Temperature .
0b = No interrupt
1b = Interrupt
4INT_LIVE0R0bInterrupt due to Boost Over Current..
0b = No interrupt
1b = Interrupt
3INT_LIVE0R0bInterrupt due to Boost MO. .
0b = No interrupt
1b = Interrupt
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.25 CHx_LIVE Register (Address = 0x3D) [Reset = 0x00]

CHx_LIVE is shown in Table 7-130.

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This register is the channel level diagnostics live status register.

Table 7-130 CHx_LIVE Register Field Descriptions
BitFieldTypeResetDescription
7STS_CHx_LIVER0bStatus of Input CH1_LIVE (INP1/INM1).
0b = No faults occurred in input channel 1
1b = Fault or Faults have occurred in input channel 1
6STS_CHx_LIVER0bStatus of Input CH2_LIVE (INP2/INM2).
0b = No faults occurred in input channel 2
1b = Fault or Faults have occurred in input channel 2
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3STS_CHx_LIVER0bStatus on fault due "Short to VBATIN fault detected when VBATIN is less than MICBIAS"
0b = Short to VBATIN fault when VBATIN is less than MICBIAS did NOT occur in any channel
1b = Short to VBATIN fault when VBATIN is less than MICBIAS has occurred in at least one channel
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.26 IN_CH1_LIVE Register (Address = 0x3E) [Reset = 0x00]

IN_CH1_LIVE is shown in Table 7-131.

Return to the Summary Table.

This register is the live status register for channel 1 input DC faults diagnostics.

Table 7-131 IN_CH1_LIVE Register Field Descriptions
BitFieldTypeResetDescription
7IN_CH1_LIVER0bInput Channel-1(INP1/INM1) Open Inputs .
0b = No Open Inputs
1b = Open Inputs
6IN_CH1_LIVER0bInput Channel-1(INP1/INM1) Inputs Shorted .
0b = No Input Shorted
1b = Input Shorted each Other
5IN_CH1_LIVER0bInput Channel-1 INP1 Shorted to GND .
0b = INP not shorted to GND
1b = INP shorted to GND
4IN_CH1_LIVER0bInput Channel-1 INM1 Shorted to GND .
0b = INM not shorted to GND
1b = INM shorted to GND
3IN_CH1_LIVER0bInput Channel-1 INP1 Shorted to MICBIAS .
0b = INP not shorted to MICBIAS
1b = INP shorted to MICBIAS
2IN_CH1_LIVER0bInput Channel-1 INM1 Shorted to MICBIAS .
0b = INM not shorted to MICBIAS
1b = INM shorted to MICBIAS
1IN_CH1_LIVER0bInput Channel-1 INP1 Shorted to VBATIN .
0b = INP not shorted to VBATIN
1b = INP shorted to VBATIN
0IN_CH1_LIVER0bInput Channel-1 INM1 Shorted to VBATIN .
0b = INM not shorted to VBATIN
1b = INM shorted to VBATIN

7.1.2.27 IN_CH2_LIVE Register (Address = 0x3F) [Reset = 0x00]

IN_CH2_LIVE is shown in Table 7-132.

Return to the Summary Table.

This register is the live status register for channel 2 input DC faults diagnostics.

Table 7-132 IN_CH2_LIVE Register Field Descriptions
BitFieldTypeResetDescription
7IN_CH2_LIVER0bInput Channel-2(INP2/INM2) Open Inputs .
0b = No Open Inputs
1b = Open Inputs
6IN_CH2_LIVER0bInput Channel-2(INP2/INM2) Inputs Shorted .
0b = No Input Shorted
1b = Input Shorted each Other
5IN_CH2_LIVER0bInput Channel-2 INP2 Shorted to GND .
0b = INP not shorted to GND
1b = INP shorted to GND
4IN_CH2_LIVER0bInput Channel-2 INM2 Shorted to GND .
0b = INM not shorted to GND
1b = INM shorted to GND
3IN_CH2_LIVER0bInput Channel-2 INP2 Shorted to MICBIAS .
0b = INP not shorted to MICBIAS
1b = INP shorted to MICBIAS
2IN_CH2_LIVER0bInput Channel-2 INM2 Shorted to MICBIAS .
0b = INM not shorted to MICBIAS
1b = INM shorted to MICBIAS
1IN_CH2_LIVER0bInput Channel-2 INP2 Shorted to VBATIN .
0b = INP not shorted to VBATIN
1b = INP shorted to VBATIN
0IN_CH2_LIVER0bInput Channel-2 INM2 Shorted to VBATIN .
0b = INM not shorted to VBATIN
1b = INM shorted to VBATIN

7.1.2.28 INT_LIVE1 Register (Address = 0x42) [Reset = 0x00]

INT_LIVE1 is shown in Table 7-133.

Return to the Summary Table.

This is the register 1 for live interrupt readback.

Table 7-133 INT_LIVE1 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LIVE1R0bChannel-1 INP1 Over Voltage .
0b = No INP Over Voltage fault
1b = INP Over Voltage fault has occurred
6INT_LIVE1R0bChannel-1 INM1 Over Voltage .
0b = No INM Over Voltage fault
1b = INM Over Voltage fault has occurred
5INT_LIVE1R0bChannel-2 INP2 Over Voltage .
0b = No INP Over Voltage fault
1b = INP Over Voltage fault has occurred
4INT_LIVE1R0bChannel-2 INM2 Over Voltage .
0b = No INM Over Voltage fault
1b = INM Over Voltage fault has occurred
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.29 INT_LIVE2 Register (Address = 0x43) [Reset = 0x00]

INT_LIVE2 is shown in Table 7-134.

Return to the Summary Table.

This is the register 2 for live interrupt readback.

Table 7-134 INT_LIVE2 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LIVE2R0bInterrupt due to GPA up threshold fault .
0b = No interrupt
1b = Interrupt
6INT_LIVE2R0bInterrupt due to GPA low threshold fault
0b = No interrupt
1b = Interrupt
5INT_LIVE2R0bInterrupt due to VAD power up detect .
0b = No interrupt
1b = Interrupt
4INT_LIVE2R0bInterrupt due to VAD power down detect .
0b = No interrupt
1b = Interrupt
3INT_LIVE2R0bInterrupt due to Micbias short circuit condition
0b = No interrupt
1b = Interrupt
2INT_LIVE2R0bInterrupt due to Micbias High current fault .
0b = No interrupt
1b = Interrupt
1INT_LIVE2R0bInterrupt due to Micbias Low current fault
0b = No interrupt
1b = Interrupt
0INT_LIVE2R0bInterrupt due to Micbias Over voltage fault .
0b = No interrupt
1b = Interrupt

7.1.2.30 DIAG_CFG0 Register (Address = 0x46) [Reset = 0x00]

DIAG_CFG0 is shown in Table 7-135.

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This is the input diagnostics configuration register 0.

Table 7-135 DIAG_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7IN_CH1_DIAG_ENR/W0bChannel-1 Input (IN1P and IN1M) Scan for Diagnostics
0b = Diagnostic Disabled
1b = Diagnostic Enabled
6IN_CH2_DIAG_ENR/W0bChannel-2 Input (IN2P and IN2M) Scan for Diagnostics
0b = Diagnostic Disabled
1b = Diagnostic Enabled
5INCL_SE_INMR/W0bINxM pin Diagnostics Scan Selection for Single Ended Configuration
0b = INxM pins of single ended channels are excluded for diagnosis
1b = INxM pins of single ended channels are included for diagnosis
4INCL_AC_COUPR/W0bAC coupled channels pins Scan Selection for Diagnostics
0b = INxP and INxM pins of AC coupled channels are excluded for diagnosis
1b = INxP and INxM pins of AC coupled channels are included for diagnosis
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.31 DIAG_CFG1 Register (Address = 0x47) [Reset = 0x37]

DIAG_CFG1 is shown in Table 7-136.

Return to the Summary Table.

This is the input diagnostics configuration register 1.

Table 7-136 DIAG_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_SHT_TERM[3:0]R/W0011bINxP and INxM Terminal Short Detect Threshold
0d = INxP and INxM Terminal Short Detect Threshold Value is 0mV
1d = INxP and INxM Terminal Short Detect Threshold Value is 30mV
2d = INxP and INxM Terminal Short Detect Threshold Value is 60mV
10d to 13d = INxP and INxM Terminal Short Detect Threshold Value is as per configuration
14d = INxP and INxM Terminal Short Detect Threshold Value is 420mV
15d = INxP and INxM Terminal Short Detect Threshold Value is 450mV
3-0DIAG_SHT_VBAT_IN[3:0]R/W0111bShort to VBATIN Detect Threshold
0d = Short to VBATIN Detect Threshold Value is 0mV
1d = Short to VBATIN Detect Threshold Value is 30mV
2d = Short to VBATIN Detect Threshold Value is 60mV
10d to 13d = Short to VBATIN Detect Threshold Value is as per configuration
14d = Short to VBATIN Detect Threshold Value is 420mV
15d = Short to VBATIN Detect Threshold Value is 450mV

7.1.2.32 DIAG_CFG2 Register (Address = 0x48) [Reset = 0x87]

DIAG_CFG2 is shown in Table 7-137.

Return to the Summary Table.

This is the input diagnostics configuration register 2.

Table 7-137 DIAG_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_SHT_GND[3:0]R/W1000bShort to GND Detect Threshold
0d = Short to GND Detect Threshold Value is 0mV
1d = Short to GND Detect Threshold Value is 60mV
2d = Short to GND Detect Threshold Value is 120mV
10d to 13d = Short to GND Detect Threshold Value is as per configuration
14d = Short to GND Detect Threshold Value is 840mV
15d = Short to GND Detect Threshold Value is 900mV
3-0DIAG_SHT_MICBIAS[3:0]R/W0111bShort to MICBIAS Detect Threshold
0d = Short to MICBIAS Detect Threshold Value is 0mV
1d = Short to MICBIAS Detect Threshold Value is 30mV
2d = Short to MICBIAS Detect Threshold Value is 60mV
10d to 13d = Short to MICBIAS Detect Threshold Value is as per configuration
14d = Short to MICBIAS Detect Threshold Value is 420mV
15d = Short to MICBIAS Detect Threshold Value is 450mV

7.1.2.33 DIAG_CFG4 Register (Address = 0x4A) [Reset = 0xB8]

DIAG_CFG4 is shown in Table 7-138.

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This is the input diagnostics configuration register 4.

Table 7-138 DIAG_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0bReserved bits; Write only reset values
5-4RESERVEDR0bReserved bits; Write only reset values
3-2FAULT_DBNCE_SEL[1:0]R/W10bDebounce count for all the faults (except VBATIN short when VBATIN < Micbias)
0b = 16 counts for debounce to filter-out false faults detection
1b = 8 counts for debounce to filter-out false faults detection
2b = 4 counts for debounce to filter-out false faults detection
3b = No debounce count
1VSHORT_DBNCER/W0bVBATIN short debounce count
0b = 16 counts for debounce to filter-out false faults detection
1b = 8 counts for debounce to filter-out false faults detection
0DIAG_2X_THRESR/W0bDiagnostic thresholds range scale
0d = Thresholds same as configured
1d = All the configuration thresholds gets scale by 2 times

7.1.2.34 DIAG_CFG5 Register (Address = 0x4B) [Reset = 0x00]

DIAG_CFG5 is shown in Table 7-139.

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This is the input diagnostics configuration register 5.

Table 7-139 DIAG_CFG5 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0bReserved bits; Write only reset values
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3RESERVEDR0bReserved bit; Write only reset value
2-0RESERVEDR0bReserved bits; Write only reset values

7.1.2.35 DIAG_CFG6 Register (Address = 0x4C) [Reset = 0xA2]

DIAG_CFG6 is shown in Table 7-140.

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This is the input diagnostics configuration register 6.

Table 7-140 DIAG_CFG6 Register Field Descriptions
BitFieldTypeResetDescription
7-0MBIAS_HIGH_CURR_THRS[7:0]R/W10100010bThreshold for Micbias High current fault diagnostics
Default = ~ 18mA
Nd = ((0.9´(N*16)/4095)-0´2)x48.46154 (mA)

7.1.2.36 DIAG_CFG7 Register (Address = 0x4D) [Reset = 0x48]

DIAG_CFG7 is shown in Table 7-141.

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This is the input diagnostics configuration register 7.

Table 7-141 DIAG_CFG7 Register Field Descriptions
BitFieldTypeResetDescription
7-0MBIAS_LOW_CURR_THRS[7:0]R/W01001000bThreshold for Micbias Low current fault diagnostics
Default = ~ 2.6mA
Nd = ((0.9´(N*16)/4095)-0´2)x48.46154 (mA)

7.1.2.37 DIAG_CFG8 Register (Address = 0x4E) [Reset = 0xBA]

DIAG_CFG8 is shown in Table 7-142.

Return to the Summary Table.

This is the input diagnostics configuration register 8.

Table 7-142 DIAG_CFG8 Register Field Descriptions
BitFieldTypeResetDescription
7-0GPA_UP_THRS_FLT_THRES[7:0]R/W10111010bGeneral Purpose Analog High Threshold
Default = ~ 2.6V
nd = ((0.9´(N*16)/4095)-0´225)x6 (V)

7.1.2.38 DIAG_CFG9 Register (Address = 0x4F) [Reset = 0x4B]

DIAG_CFG9 is shown in Table 7-143.

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This is the input diagnostics configuration register 9.

Table 7-143 DIAG_CFG9 Register Field Descriptions
BitFieldTypeResetDescription
7-0GPA_LOW_THRS_FLT_THRES[7:0]R/W01001011bGeneral Purpose Analog Low Threshold
Default = ~ 0.2V
nd = ((0.9´(N*16)/4095)-0´225)x6 (V)

7.1.2.39 DIAG_CFG10 Register (Address = 0x50) [Reset = 0x88]

DIAG_CFG10 is shown in Table 7-144.

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This is the input diagnostics configuration register 10.

Table 7-144 DIAG_CFG10 Register Field Descriptions
BitFieldTypeResetDescription
7PD_MBIAS_SHRT_CKT_FLTR/W1bPower down configuration of Micbias during Short Circuit fault
0b = No change when fault occurs
1b = Micbias is disabled when fault occurs
6PD_MBIAS_HIGH_CURR_FLTR/W0bPower down configuration of Micbias during High current fault
0b = No change when fault occurs
1b = Micbias is disabled when fault occurs
5PD_MBIAS_LOW_CURR_FLTR/W0bPower down configuration of Micbias during Low current fault
0b = No change when fault occurs
1b = Micbias is disabled when fault occurs
4PD_MBIAS_OV_FLTR/W0bPower down configuration of Micbias during high voltage fault
0b = No change when fault occurs
1b = Micbias is disabled when fault occurs
3PD_MBIAS_OT_FLTR/W1bPower down configuration of Micbias during over temperature fault
0b = No change when fault occurs
1b = Micbias is disabled when fault occurs
2MAN_RCV_PD_FLT_CHKR/W0bManual Recovery (self clear bit)
0b = No effect
1b = Recheck fault status and re-powerup channels if the channels do not have any faults
1MBIAS_FLT_AUTO_REC_ENR/W0bMicbias PD on faults Auto-Recovery Enable
0d = Auto recovery from Micbias faults disabled
1d = Auto recovery enabled
0MICBIAS_SHRT_CKT_DET_DISR/W0b Micbias Short Circuit fault detect config
0b = enable
1b = disable

7.1.2.40 DIAG_CFG11 Register (Address = 0x51) [Reset = 0x40]

DIAG_CFG11 is shown in Table 7-145.

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This is the input diagnostics configuration register 11.

Table 7-145 DIAG_CFG11 Register Field Descriptions
BitFieldTypeResetDescription
7-5SAFEBAND_MBIAS_OV_FLT[2:0]R/W010bSafe band cfgn for Micbias over voltage fault's lower boundary
0 = No safe band
1 = 30mV safe band (1LSb at 9b lvl)
2 = 60mV safe band (2LSb at 9b lvl)
3-7 = N*30mV
4-0RESERVEDR0bReserved bits; Write only reset values

7.1.2.41 DIAG_CFG12 Register (Address = 0x52) [Reset = 0x44]

DIAG_CFG12 is shown in Table 7-146.

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This is the input diagnostics configuration register 12.

Table 7-146 DIAG_CFG12 Register Field Descriptions
BitFieldTypeResetDescription
7-5SAFEBAND_INx_MBIAS_FLT[2:0]R/W010bSafe band cfgn for INx Short to Micbias fault's upper boundary
0 = No safe band
1 = 30mV safe band (1LSb at 9b lvl)
2 = 60mV safe band (2LSb at 9b lvl)
3-7 = N*30mV
4-2SAFEBAND_INx_OV_FLT[2:0]R/W001bSafe band cfgn for INx Overvoltage fault's lower boundary
0 = No safe band
1 = 30mV safe band (1LSb at 9b lvl)
2-7 = N*30mV
1-0RESERVEDR0bReserved bits; Write only reset values

7.1.2.42 DIAG_CFG13 Register (Address = 0x53) [Reset = 0x00]

DIAG_CFG13 is shown in Table 7-147.

Return to the Summary Table.

This is the input diagnostics configuration register 13.

Table 7-147 DIAG_CFG13 Register Field Descriptions
BitFieldTypeResetDescription
7DIAG_FORCE_ENR/W0bConfiguration for auto/manual enable for diag vbat, micbias, micbias load, temp
0b = Auto enabled (auto enabled if at least one of the input channel diagnostics is enabled in DIAG_CFG0)
1b = Manual en/disable based on DIAG_CFG13 Register
6DIAG_EN_MICBIAS_LOADR/W0bMicbias current/load channel enable for Diagnostics, valid if DIAG_FORCE_EN = 1
0b = Diagnostic Disabled
1b = Diagnostic Enabled
5DIAG_EN_MICBIASR/W0bMicbias channel enable for Diagnostics, valid if DIAG_FORCE_EN = 1
0b = Diagnostic Disabled
1b = Diagnostic Enabled
4DIAG_EN_VBATR/W0bVBAT channel enable for Diagnostics, valid if DIAG_FORCE_EN = 1
0b = Diagnostic Disabled
1b = Diagnostic Enabled
3DIAG_EN_TEMP_SENSER/W0bTemp sense channel enable for Diagnostics, valid if DIAG_FORCE_EN = 1
0b = Diagnostic Disabled
1b = Diagnostic Enabled
2DIAG_EN_AVDDR/W0bAVDD channel enable for Diagnostics
0b = Diagnostic Disabled
1b = Diagnostic Enabled
1DIAG_EN_GPAR/W0bGPA channel enable for Diagnostics
0b = Diagnostic Disabled
1b = Diagnostic Enabled
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.43 DIAG_CFG14 Register (Address = 0x54) [Reset = 0x48]

DIAG_CFG14 is shown in Table 7-148.

Return to the Summary Table.

This is the input diagnostics configuration register 14.

Table 7-148 DIAG_CFG14 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5AVDD_FILT_SEL[1:0]R/W10bAVDD filter select
0d = 3.5MHz
1d = 200kHz
2d = 100kHz
3d = No filter
4RESERVEDR0bReserved bit; Write only reset value
3-2VBAT_FILT_SEL[1:0]R/W10bVBAT filter select
0d = 3.5MHz
1d = 200kHz
2d = 100kHz
3d = No filter
1RESERVEDR0bReserved bit; Write only reset value
0VBAT_SHRT_FLTR/W0bCfgn on INx short to VBAT
0 = INx Overvoltage and INx short to VBAT are separate
1 = INx Overvoltage and INx short to VBAT are Ord together as VBAT short fault

7.1.2.44 DIAGDATA_CFG Register (Address = 0x55) [Reset = 0x00]

DIAGDATA_CFG is shown in Table 7-149.

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This register is the input diagnostics data configuration register.

Table 7-149 DIAGDATA_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0bReserved bits; Write only reset values
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1OVRD_VBAT_TEMP_DATAR/W0bOverride VBAT and TEMP data
0b= Override Disabled
1b= Override Enabled
0HOLD_SAR_DATAR/W0bHold SAR data update during register readback
0b= Data update is not held, Data register is continuously updated
1b= Data update is held, Data register readback can be done

7.1.2.45 DIAG_MON_MSB_VBAT Register (Address = 0x56) [Reset = 0x00]

DIAG_MON_MSB_VBAT is shown in Table 7-150.

Return to the Summary Table.

This register is the diagnostics SAR VBATIN monitor data MSB byte register.

Table 7-150 DIAG_MON_MSB_VBAT Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_VBAT[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.46 DIAG_MON_LSB_VBAT Register (Address = 0x57) [Reset = 0x00]

DIAG_MON_LSB_VBAT is shown in Table 7-151.

Return to the Summary Table.

This register is the diagnostics SAR VBATIN monitor data LSB nibble register.

Table 7-151 DIAG_MON_LSB_VBAT Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_VBAT[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R0000bChannel ID

7.1.2.47 DIAG_MON_MSB_MBIAS Register (Address = 0x58) [Reset = 0x00]

DIAG_MON_MSB_MBIAS is shown in Table 7-152.

Return to the Summary Table.

This register is the diagnostics SAR MICBIAS monitor data MSB byte register.

Table 7-152 DIAG_MON_MSB_MBIAS Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_MBIAS[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.48 DIAG_MON_LSB_MBIAS Register (Address = 0x59) [Reset = 0x01]

DIAG_MON_LSB_MBIAS is shown in Table 7-153.

Return to the Summary Table.

This register is the diagnostics SAR MICBIAS monitor data LSB nibble.

Table 7-153 DIAG_MON_LSB_MBIAS Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_MBIAS[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R0001bChannel ID

7.1.2.49 DIAG_MON_MSB_IN1P Register (Address = 0x5A) [Reset = 0x00]

DIAG_MON_MSB_IN1P is shown in Table 7-154.

Return to the Summary Table.

This register is the diagnostics SAR IN1P monitor data MSB byte register.

Table 7-154 DIAG_MON_MSB_IN1P Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_IN_CH1P[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.50 DIAG_MON_LSB_IN1P Register (Address = 0x5B) [Reset = 0x02]

DIAG_MON_LSB_IN1P is shown in Table 7-155.

Return to the Summary Table.

This register is the diagnostics SAR IN1P monitor data LSB nibble register.

Table 7-155 DIAG_MON_LSB_IN1P Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_IN_CH1P[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R0010bChannel ID

7.1.2.51 DIAG_MON_MSB_IN1M Register (Address = 0x5C) [Reset = 0x00]

DIAG_MON_MSB_IN1M is shown in Table 7-156.

Return to the Summary Table.

This register is the diagnostics SAR IN1M monitor data MSB byte register.

Table 7-156 DIAG_MON_MSB_IN1M Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_IN_CH1N[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.52 DIAG_MON_LSB_IN1M Register (Address = 0x5D) [Reset = 0x03]

DIAG_MON_LSB_IN1M is shown in Table 7-157.

Return to the Summary Table.

This register is the diagnostics SAR IN1M monitor data LSB nibble register.

Table 7-157 DIAG_MON_LSB_IN1M Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_IN_CH1N[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R0011bChannel ID

7.1.2.53 DIAG_MON_MSB_IN2P Register (Address = 0x5E) [Reset = 0x00]

DIAG_MON_MSB_IN2P is shown in Table 7-158.

Return to the Summary Table.

This register is the diagnostics SAR IN2P monitor data MSB byte register.

Table 7-158 DIAG_MON_MSB_IN2P Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_IN_CH2P[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.54 DIAG_MON_LSB_IN2P Register (Address = 0x5F) [Reset = 0x04]

DIAG_MON_LSB_IN2P is shown in Table 7-159.

Return to the Summary Table.

This register is the diagnostics SAR IN2P monitor data LSB nibble register.

Table 7-159 DIAG_MON_LSB_IN2P Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_IN_CH2P[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R0100bChannel ID

7.1.2.55 DIAG_MON_MSB_IN2M Register (Address = 0x60) [Reset = 0x00]

DIAG_MON_MSB_IN2M is shown in Table 7-160.

Return to the Summary Table.

This register is the diagnostics SAR IN2M monitor data MSB byte register.

Table 7-160 DIAG_MON_MSB_IN2M Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_IN_CH2N[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.56 DIAG_MON_LSB_IN2M Register (Address = 0x61) [Reset = 0x05]

DIAG_MON_LSB_IN2M is shown in Table 7-161.

Return to the Summary Table.

This register is the diagnostics SAR IN2M monitor data LSB nibble register.

Table 7-161 DIAG_MON_LSB_IN2M Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_IN_CH2N[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R0101bChannel ID

7.1.2.57 DIAG_MON_MSB_TEMP Register (Address = 0x6A) [Reset = 0x00]

DIAG_MON_MSB_TEMP is shown in Table 7-162.

Return to the Summary Table.

This register is the diagnostics SAR Temperature monitor data MSB byte register.

Table 7-162 DIAG_MON_MSB_TEMP Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_TEMP[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.58 DIAG_MON_LSB_TEMP Register (Address = 0x6B) [Reset = 0x0A]

DIAG_MON_LSB_TEMP is shown in Table 7-163.

Return to the Summary Table.

This register is the diagnostics SAR Temperature monitor data LSB nibble register.

Table 7-163 DIAG_MON_LSB_TEMP Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_TEMP[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1010bChannel ID

7.1.2.59 DIAG_MON_MSB_MBIAS_LOAD Register (Address = 0x6C) [Reset = 0x00]

DIAG_MON_MSB_MBIAS_LOAD is shown in Table 7-164.

Return to the Summary Table.

This register is the diagnostics SAR MICBIAS LOAD Current monitor data MSB byte register.

Table 7-164 DIAG_MON_MSB_MBIAS_LOAD Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_MBIAS_LOAD[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.60 DIAG_MON_LSB_MBIAS_LOAD Register (Address = 0x6D) [Reset = 0x0B]

DIAG_MON_LSB_MBIAS_LOAD is shown in Table 7-165.

Return to the Summary Table.

This register is the diagnostic SAR MICBIAS LOAD Current monitor data LSB nibble register.

Table 7-165 DIAG_MON_LSB_MBIAS_LOAD Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_MBIAS_LOAD[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1011bChannel ID

7.1.2.61 DIAG_MON_MSB_AVDD Register (Address = 0x6E) [Reset = 0x00]

DIAG_MON_MSB_AVDD is shown in Table 7-166.

Return to the Summary Table.

This register is the diagnostic SAR AVDD monitor data MSB byte register.

Table 7-166 DIAG_MON_MSB_AVDD Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_AVDD[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.62 DIAG_MON_LSB_AVDD Register (Address = 0x6F) [Reset = 0x0C]

DIAG_MON_LSB_AVDD is shown in Table 7-167.

Return to the Summary Table.

This register is the diagnostic SAR AVDD monitor data LSB nibble register

Table 7-167 DIAG_MON_LSB_AVDD Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_AVDD[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1100bChannel ID

7.1.2.63 DIAG_MON_MSB_GPA Register (Address = 0x70) [Reset = 0x00]

DIAG_MON_MSB_GPA is shown in Table 7-168.

Return to the Summary Table.

This register is the diagnostic SAR GPA monitor data MSB byte register.

Table 7-168 DIAG_MON_MSB_GPA Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_GPA[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.64 DIAG_MON_LSB_GPA Register (Address = 0x71) [Reset = 0x0D]

DIAG_MON_LSB_GPA is shown in Table 7-169.

Return to the Summary Table.

This register is the diagnostic SAR GPA monitor data LSB nibble register.

Table 7-169 DIAG_MON_LSB_GPA Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_GPA[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1101bChannel ID

7.1.2.65 BOOST_CFG Register (Address = 0x72) [Reset = 0x00]

BOOST_CFG is shown in Table 7-170.

Return to the Summary Table.

This register is the boost configuration register.

Table 7-170 BOOST_CFG Register Field Descriptions
BitFieldTypeResetDescription
7BOOST_DISR/W0bBoost Enable/Disable
0d = Internal Boost enable
1d = Internal Boost disable/bypass
6RESERVEDR0bReserved bit; Write only reset value
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3RESERVEDR0bReserved bit; Write only reset value
2-0RESERVEDR0bReserved bits; Write only reset values

7.1.2.66 MICBIAS_CFG Register (Address = 0x73) [Reset = 0xA0]

MICBIAS_CFG is shown in Table 7-171.

Return to the Summary Table.

This register is the micbias configuration register.

Table 7-171 MICBIAS_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-4MICBIAS_VAL[3:0]R/W1010bMicbias Value
0d = Microphone Bias output is bypassed to BSTOUT/HVDD
1d = Microphone Bias is set to 3.0V
2d = Microphone Bias is set to 3.5V
3d = Microphone Bias is set to 4.0V
4d = Microphone Bias is set to 4.5V
5d = Microphone Bias is set to 5V
6d = Microphone Bias is set to 5.5V
7d = Microphone Bias is set to 6V
8d = Microphone Bias is set to 6.5V
9d = Microphone Bias is set to 7V
10d = Microphone Bias is set to 7.5V
11d = Microphone Bias is set to 8V
12d = Microphone Bias is set to 8.5V
13d = Microphone Bias is set to 9V
14d = Microphone Bias is set to 9.5V
15d = Microphone Bias is set to 10V
3-0RESERVEDR0bReserved bits; Write only reset value