SLASFD0A December   2024  – June 2025 MSPM0L1116-Q1 , MSPM0L1117-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
    3. 6.3 Signal Descriptions
      1.      13
      2.      14
      3.      15
      4.      16
      5.      17
      6.      18
      7.      19
      8.      20
      9.      21
      10.      22
      11.      23
      12.      24
      13.      25
      14.      26
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 Low Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 I2C
      1. 7.15.1 I2C Characteristics
      2. 7.15.2 I2C Filter
      3. 7.15.3 I2C Timing Diagram
    16. 7.16 SPI
      1. 7.16.1 SPI
      2. 7.16.2 SPI Timing Diagram
    17. 7.17 UART
    18. 7.18 TIMx
    19. 7.19 TRNG Electrical Characteristics
    20. 7.20 TRNG Switching Characteristics
    21. 7.21 Emulation and Debug
      1. 7.21.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Functional Block Diagram
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode
    4. 8.4  Power Management Unit (PMU)
    5. 8.5  Clock Module (CKM)
    6. 8.6  DMA
    7. 8.7  Events
    8. 8.8  Memory
      1. 8.8.1 Memory Organization
      2. 8.8.2 Peripheral File Map
      3. 8.8.3 Peripheral Interrupt Vector
    9. 8.9  Flash Memory
    10. 8.10 SRAM
    11. 8.11 GPIO
    12. 8.12 IOMUX
    13. 8.13 ADC
    14. 8.14 Temperature Sensor
    15. 8.15 VREF
    16. 8.16 Security
    17. 8.17 TRNG
    18. 8.18 AESADV
    19. 8.19 Keystore
    20. 8.20 CRC-P
    21. 8.21 UART
    22. 8.22 I2C
    23. 8.23 SPI
    24. 8.24 Low-Frequency Sub System (LFSS)
    25. 8.25 RTC_B
    26. 8.26 IWDT_B
    27. 8.27 WWDT
    28. 8.28 Timers (TIMx)
    29. 8.29 Device Analog Connections
    30. 8.30 Input/Output Diagrams
    31. 8.31 Serial Wire Debug Interface
    32. 8.32 Bootstrap Loader (BSL)
    33. 8.33 Device Factory Constants
    34. 8.34 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

1 Features

  • Core
    • Arm® 32-bit Cortex®-M0+ CPU with memory protection unit, frequency up to 32MHz
  • Functional Safety-Capable
    • Documentation will be available to aid functional safety system design
  • PSA-L1 Certification targeted
  • Operating characteristics
    • Extended temperature: –40°C to 125°C
    • Wide supply voltage range: 1.62V to 3.6V
  • Memories
    • Up to 128KB of flash memory with error correction code (ECC)

      • Dual-bank with address swap for OTA updates

    • 16KB of SRAM
  • High-performance analog peripherals
    • One 12-bit 1.68Msps analog-to-digital converter (ADC) with up to 13 external channels
      • 14-bit effective resolution at 105ksps with hardware averaging
    • Configurable 1.4V or 2.5V internal voltage reference (VREF)
    • Integrated temperature sensor
  • Optimized low-power modes
    • RUN: 106µA/MHz (CoreMark)
    • SLEEP: 50µA/MHz
    • STOP: 239µA at 4MHz
    • STANDBY: 1.5µA at 32kHz with RTC and full SRAM and state retention
    • SHUTDOWN: 75nA with IO wake-up capability
  • Intelligent digital peripherals
    • 3-channel DMA controller
    • 3-channel event fabric signaling system

    • A total of 14 PWM channels supported by:

      • One 16-bit advanced timer with deadband support and complimentary outputs up to 8 PWM channels

      • Two 16-bit general-purpose timers support low-power operation in STANDBY mode
      • One 16-bit general purpose timer supporting QEI
    • One windowed watchdog timer (WWDT)
    • One independent watchdog timer (IWDT)
    • RTC with alarm and calendar mode
  • Enhanced communication interfaces

    • Two UART interfaces supporting low-power operation in STANDBY mode

      • One supporting LIN, IrDA, DALI, Smart Card, Manchester
    • One I2C interface supporting up to FM+ (1Mbit/s), SMBus/PMBus, and wakeup from STOP mode
    • One SPI interface supporting up to 16Mbit/s
  • Clock system
    • Internal 4 to 32MHz oscillator (SYSOSC) with up to ±1.2% accuracy
    • Internal 32kHz low-frequency oscillator (LFOSC) with ±3% accuracy
    • External 32-kHz crystal oscillator (LFXT)
  • Data integrity and encryption
    • AES-128/256 accelerator with support for GCM/GMAC, CCM/CBC-MAC, CBC, CTR
    • Secure key storage for up to two AES keys
    • Flexible firewalls for protecting code and data
    • True random number generator (TRNG)
    • Cyclic redundancy checker (CRC-16, CRC-32)
  • Flexible I/O features
    • Up to 44 GPIOs
      • Two 5V-tolerant open-drain IOs
      • Seven high-drive IOs with 20mA drive strength
      • One high-speed IO
  • Development support
    • 2-pin serial wire debug (SWD)
  • Package options
    • 48-pin LQFP (PT) (0.5mm pitch)
    • 48-pin VQFN (RGZ) (0.5mm pitch, wettable flank)
    • 32-pin VQFN (RHB) (0.5mm pitch, wettable flank)
    • 24-pin VQFN (RGE) (0.5mm pitch, wettable flank)
  • Family members (also see Device Comparison)
    • MSPM0L1116-Q1: 64KB of flash, 16KB of RAM
    • MSPM0L1117-Q1: 128KB of flash, 16KB of RAM
  • Development kits and software (also see Tools and Software)
    • LP-MSPM0L1117 LaunchPad™ development kit
    • MSP Software Development Kit (SDK)
  • Automotive qualification
    • AEC-Q100 Grade 1 (-40°C to 125°C)
    • Wettable flank for 24-pin, 32-pin, and 48-pin VQFN options