SLASFD0A December   2024  – June 2025 MSPM0L1116-Q1 , MSPM0L1117-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
    3. 6.3 Signal Descriptions
      1.      13
      2.      14
      3.      15
      4.      16
      5.      17
      6.      18
      7.      19
      8.      20
      9.      21
      10.      22
      11.      23
      12.      24
      13.      25
      14.      26
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 Low Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 I2C
      1. 7.15.1 I2C Characteristics
      2. 7.15.2 I2C Filter
      3. 7.15.3 I2C Timing Diagram
    16. 7.16 SPI
      1. 7.16.1 SPI
      2. 7.16.2 SPI Timing Diagram
    17. 7.17 UART
    18. 7.18 TIMx
    19. 7.19 TRNG Electrical Characteristics
    20. 7.20 TRNG Switching Characteristics
    21. 7.21 Emulation and Debug
      1. 7.21.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Functional Block Diagram
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode
    4. 8.4  Power Management Unit (PMU)
    5. 8.5  Clock Module (CKM)
    6. 8.6  DMA
    7. 8.7  Events
    8. 8.8  Memory
      1. 8.8.1 Memory Organization
      2. 8.8.2 Peripheral File Map
      3. 8.8.3 Peripheral Interrupt Vector
    9. 8.9  Flash Memory
    10. 8.10 SRAM
    11. 8.11 GPIO
    12. 8.12 IOMUX
    13. 8.13 ADC
    14. 8.14 Temperature Sensor
    15. 8.15 VREF
    16. 8.16 Security
    17. 8.17 TRNG
    18. 8.18 AESADV
    19. 8.19 Keystore
    20. 8.20 CRC-P
    21. 8.21 UART
    22. 8.22 I2C
    23. 8.23 SPI
    24. 8.24 Low-Frequency Sub System (LFSS)
    25. 8.25 RTC_B
    26. 8.26 IWDT_B
    27. 8.27 WWDT
    28. 8.28 Timers (TIMx)
    29. 8.29 Device Analog Connections
    30. 8.30 Input/Output Diagrams
    31. 8.31 Serial Wire Debug Interface
    32. 8.32 Bootstrap Loader (BSL)
    33. 8.33 Device Factory Constants
    34. 8.34 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

11 Revision History

Changes from December 1, 2024 to May 31, 2025 (from Revision * (December 2024) to Revision A (June 2025))

  • Corrected list of I/O featuresGo
  • Added note to indicate that this device is targeting PSA-L1 certificationGo
  • Updated Device Comparison section to tabulate communication peripheral instancesGo
  • Updated Pin Attributes section to correctly list IO types available in this device, and added footnote indicating SDIO with wake functionalityGo
  • Corrected Pin Attributes tables to indicate that GPIO PA2 is controlled by PINCM7 instead of PINCM61Go
  • Corrected Pin Attributes tables to indicate that PA15 is a High-drive type IO (HDIO)Go
  • Corrected Pin Attributes tables to indicate that PB24 is a standard type IO (SDIO)Go
  • Updated Absolute Maximum Ratings for I_VDD and I_VSS to reflect correct junction temperatures and also remove VDD>=2.7V conditionGo
  • Added diode current rating for PB24 to Absolute Maximum RatingsGo
  • Added ambient temperature rating to Absolute Maximum RatingsGo
  • Added footnote to I_VDD and I_VSS guidelines for reduced current consumption when VDD supply voltage is low (e.g. 1.62V)Go
  • Updated Supply Current Characteristics to include maximum values and accurate typical valuesGo
  • Added Supply Current Characteristics parameter for per-MHz SLEEP current (assessed at 32MHz)Go
  • Changed POR and BOR specifications to reflect accurate voltage thresholds for POR and coldboot BORGo
  • Updated POR and BOR specifications section to remove footnote for dVDD/dt conditionGo
  • Changed Flash Memory Characteristics to allow for users to designate any 32kB sectors of flash memory to apply 100k cycles, rather than only the lower 32kB sectorsGo
  • Updated Timing Characteristics section with accurate specification values and corrected spec label for Wakeup time from STOP1 and STOP2 to RUNGo
  • Updated System Oscillator specifications with accurate valuesGo
  • Removed SYSOSC Typical Frequency Accuracy FigureGo
  • Removed LFXT specification for VDD power supply range, as specifications were already applicable for entire VDD operating range of the deviceGo
  • Changed LFXT start-up time to indicate typical value of 1 secondGo
  • Updated Digital IO electrical characteristics to reflect ambient temperature conditionsGo
  • Added rise/fall time specifications to Digital IO switching characteristicsGo
  • Added footnote for HDIO DRV=1 condition to limit signal slew rate for high current operationGo
  • Updated ADC specifications for SNR and PSRRDC to remove minimum valuesGo
  • Updated Temperature Sensor coefficient specification valuesGo
  • Changed VREF electrical characteristics for I_VREF, TC_VREF, and PSRRDC specification valuesGo
  • Removed Vnoise specifications from VREF electrical characteristicsGo
  • Updated SPI specifications to reflect corrected setup and hold timing valuesGo
  • Updated CPU description section to indicate support for memory protection unit (MPU)Go
  • Updated Supported Functionality by Operating Mode table for accuracy and organizationGo
  • Added detailed DMA Features table to DMA sectionGo
  • Updated Flash Memory section to indicate that any 32kB sectors can be selected for high-endurance operationGo
  • Updated description in SRAM section regarding write-execute user operationGo
  • Updated GPIO section to clarify that there are two GPIO ports in this device (PAx and PBx)Go
  • Updated Temperature Sensor section to add details for per-unit TSc calculation method using V_TRIM_0KGo
  • Updated VREF section to clarify that the VREF in this device does not require a decoupling capacitor on VREF+/- pins for proper operation, and also added a block diagram detailing VREF configurations. Go
  • Updated Security section to list all security features present in this deviceGo
  • Updated SPI section to reference MCLK rather than ULPCLKGo
  • Updated LFSS section to indicate presence of LFSS_B and RTC_B variantsGo
  • Updated Timers section to correctly detail capabilities of various timer instance typesGo
  • Updated Mechanical, Packaging, and Orderable Information section to append drawings for each package variantGo