SLASFD0A December 2024 – June 2025 MSPM0L1116-Q1 , MSPM0L1117-Q1
PRODUCTION DATA
MSPM0L111x-Q1 MCUs include a low power, high performance SRAM memory with zero wait state access across the supported CPU frequency range of the device. MSPM0 MCUs also provide up to 16KB SRAM. SRAM memory may be used for storing volatile information such as the call stack, heap, global data, and code.
The SRAM memory content is fully retained in run, sleep, stop, and standby operating modes and is lost in shutdown mode.
A write-execute mutual exclusion mechanism is provided to allow the application to partition the SRAM into two sections: a read-write (RW) partition and a read-execute (RX) partition. The SRAMBOUNDARY register in SYSCTL needs to be configured to set up these partitions. The RX partition occupies the upper portion of the SRAM address space. Write protection is useful when placing executable code into SRAM as it provides a level of protection against unintentional overwrites of code by either the CPU or DMA. Placing code in SRAM can improve performance of critical loops by enabling zero wait state operation and lower power consumption. Preventing code execution from the RW partition improves security by preventing self-modifying code execution ability.