SLASFN5 December   2025 MSPM0L1126 , MSPM0L1127 , MSPM0L2116 , MSPM0L2117

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      10
    3. 6.3 Signal Descriptions
      1.      12
      2.      13
      3.      14
      4.      15
      5.      16
      6.      17
      7.      18
      8.      19
      9.      20
      10.      21
      11.      22
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 Low Frequency Crystal/Clock
      4. 7.9.4 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Linearity Parameters
      3. 7.12.3 Switching Characteristics
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Electrical Characteristics
      2. 7.14.2 Voltage Characteristics
    15. 7.15 Comparator (COMP)
      1. 7.15.1 Comparator Electrical Characteristics
    16. 7.16 LCD
    17. 7.17 I2C
      1. 7.17.1 I2C Characteristics
      2. 7.17.2 I2C Filter
      3. 7.17.3 I2C Timing Diagram
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 Emulation and Debug
      1. 7.21.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA Trigger Mapping
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripherals Summary
      3. 8.7.3 Interrupt Vector Number
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 LFSS
    15. 8.15 IWDT
    16. 8.16 RTC_B
    17. 8.17 VREF
    18. 8.18 COMP
    19. 8.19 Security
    20. 8.20 AESADV
    21. 8.21 CRC
    22. 8.22 Keystore
    23. 8.23 UNICOMM (UART/I2C/SPI)
      1. 8.23.1 UART (UNICOMM)
      2. 8.23.2 I2C (UNICOMM)
      3. 8.23.3 SPI (UNICOMM)
    24. 8.24 WWDT
    25. 8.25 Timers (TIMx)
    26. 8.26 LCD
    27. 8.27 Device Analog Connections
    28. 8.28 Input/Output Diagrams
    29. 8.29 DEBUGSS
    30. 8.30 Serial Wire Debug Interface
    31. 8.31 Bootstrap Loader (BSL)
    32. 8.32 Device Factory Constants
    33. 8.33 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

7.5.1 RUN/SLEEP Modes

VDD=3.3V. All inputs tied to 0V or VDD. Outputs do not source or sink any current. All peripherals are disabled.
PARAMETER MCLK -40°C 25°C 85°C 105°C 125°C UNIT
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
RUN Mode
IDDRUN MCLK=SYSOSC, CoreMark, execute from flash 32MHz 3.1 3.1 3.1 3.2 3.2 mA
IDDRUN, per MHz MCLK=SYSOSC, While(1), execute from flash 32MHz 52 59 52 59 53 59 53 59 54 60 uA/Mhz
MCLK=SYSOSC, CoreMark, execute from flash 32MHz 97 98 98 98 99
SLEEP Mode
IDDSLEEP MCLK=SYSOSC, CPU is halted 32MHz 1265 1426 1284 1429 1310 1481 1317 1488 1329 1472 uA
IDDSLEEP MCLK=LFCLK, CPU is halted 32kHz 262 303 266 304 299 358 307 366 322 381 uA