SLASFO8 July   2025 AFE53004W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics, Voltage Output
    6. 5.6  Electrical Characteristics, Current Output
    7. 5.7  Electrical Characteristics, Comparator Mode
    8. 5.8  Electrical Characteristics, ADC Input
    9. 5.9  Electrical Characteristics, General
    10. 5.10 Timing Requirements, I2C Standard Mode
    11. 5.11 Timing Requirements, I2C Fast Mode
    12. 5.12 Timing Requirements, I2C Fast Mode Plus
    13. 5.13 Timing Requirements, SPI Write Operation
    14. 5.14 Timing Requirements, SPI Read and Daisy Chain Operation (FSDO = 0)
    15. 5.15 Timing Requirements, SPI Read and Daisy Chain Operation (FSDO = 1)
    16. 5.16 Timing Requirements, GPIO
    17. 5.17 Timing Diagrams
    18. 5.18 Typical Characteristics: Voltage Output
    19. 5.19 Typical Characteristics: Current Output
    20. 5.20 Typical Characteristics: ADC
    21. 5.21 Typical Characteristics: Comparator
    22. 5.22 Typical Characteristics: General
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Smart Analog-Front-End Converter (AFE) Architecture
      2. 6.3.2 Digital Input/Output
      3. 6.3.3 Nonvolatile Memory (NVM)
    4. 6.4 Device Functional Modes
      1. 6.4.1  Voltage-Output Mode
        1. 6.4.1.1 Voltage Reference and DAC Transfer Function
          1. 6.4.1.1.1 Internal Reference
          2. 6.4.1.1.2 External Reference
          3. 6.4.1.1.3 Power-Supply as Reference
      2. 6.4.2  Current-Output Mode
      3. 6.4.3  Analog-to-Digital Converter (ADC) Mode
      4. 6.4.4  Comparator Mode
        1. 6.4.4.1 Programmable Hysteresis Comparator
        2. 6.4.4.2 Programmable Window Comparator
      5. 6.4.5  Programmable Slew-Rate Control
      6. 6.4.6  Fault-Dump Mode
      7. 6.4.7  High-Impedance Output and PROTECT Input
      8. 6.4.8  PMBus Compatibility Mode
      9. 6.4.9  Function Generation
        1. 6.4.9.1 Triangular Waveform Generation
        2. 6.4.9.2 Sawtooth Waveform Generation
        3. 6.4.9.3 Sine Waveform Generation
      10. 6.4.10 Device Reset and Fault Management
        1. 6.4.10.1 Power-On Reset (POR)
        2. 6.4.10.2 External Reset
        3. 6.4.10.3 Register-Map Lock
        4. 6.4.10.4 NVM Cyclic Redundancy Check (CRC)
          1. 6.4.10.4.1 NVM-CRC-FAIL-USER Bit
          2. 6.4.10.4.2 NVM-CRC-FAIL-INT Bit
      11. 6.4.11 Power-Down Mode
    5. 6.5 Programming
      1. 6.5.1 SPI Programming Mode
      2. 6.5.2 I2C Programming Mode
        1. 6.5.2.1 F/S Mode Protocol
        2. 6.5.2.2 I2C Update Sequence
          1. 6.5.2.2.1 Address Byte
          2. 6.5.2.2.2 Command Byte
        3. 6.5.2.3 I2C Read Sequence
      3. 6.5.3 General-Purpose Input/Output (GPIO) Modes
  8. 7 Register Map
    1. 7.1  NOP Register (address = 00h) [reset = 0000h]
    2. 7.2  DAC-X-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
    3. 7.3  DAC-X-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
    4. 7.4  DAC-X-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0000h]
    5. 7.5  DAC-X-IOUT-MISC-CONFIG Register (address = 04h, 0Ah, 10h, 16h) [reset = 0000h]
    6. 7.6  DAC-X-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
    7. 7.7  DAC-X-FUNC-CONFIG Register (address = 06h, 0Ch, 12h, 18h) [reset = 0000h]
    8. 7.8  DAC-X-DATA Register (address = 19h, 1Ah, 1Bh, 1Ch) [reset = 0000h]
    9. 7.9  ADC-CONFIG-TRIG Register (address = 1Dh) [reset = 0000h]
    10. 7.10 ADC-DATA Register (address = 1Eh) [reset = 0000h]
    11. 7.11 COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
    12. 7.12 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
    13. 7.13 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
    14. 7.14 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
    15. 7.15 CMP-STATUS Register (address = 23h) [reset = 0000h]
    16. 7.16 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
    17. 7.17 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
    18. 7.18 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
    19. 7.19 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
    20. 7.20 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
    21. 7.21 DAC-X-DATA-8BIT Register (address = 40h, 41h, 42h, 43h) [reset = 0000h]
    22. 7.22 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
    23. 7.23 PMBUS-PAGE Register [reset = 0300h]
    24. 7.24 PMBUS-OP-CMD-X Register [reset = 0000h]
    25. 7.25 PMBUS-CML Register [reset = 0000h]
    26. 7.26 PMBUS-VERSION Register [reset = 2200h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

Figure 4-1 YBH Package, 16-Pin DSBGA (Top View)
Table 4-1 Pin Functions
PINTYPEDESCRIPTION
NO.NAME
A1VREFPowerExternal reference input. Connect a capacitor (approximately 0.1μF) between VREF and AGND.
Use a pullup resistor to VDD when the external reference is not used. Do not ramp up this pin before VDD. If an external reference is used, ensure that the reference ramps up after VDD.
A2OUT3/ADCOutputAnalog output from DAC channel 3 in voltage- or current-output mode. Input to ADC channel 3 in ADC mode.
A3OUT2OutputAnalog output from DAC channel 2. Not connected in ADC mode; leave floating.
A4GPIO/SDOInput/OutputGeneral-purpose input/output configurable as LDAC, PD, PROTECT, RESET, SDO, and STATUS. For STATUS and SDO, connect the pin to the IO voltage with an external pullup resistor. If unused, connect the GPIO pin to VDD or AGND using an external resistor. This pin is able to ramp up before VDD.
B1VDDPowerSupply voltage.
B2FB3/AENInputVoltage feedback pin for channel 3. In voltage-output mode, connect to OUT3 for closed-loop amplifier output. In current-output mode, keep the FB3 pin unconnected to minimize leakage current. In ADC mode, connect to VDD with a pullup resistor.
B3FB2/AIN2InputVoltage feedback pin for channel 2. In voltage-output mode, connect to OUT2 for closed-loop amplifier output. In current-output mode, keep the FB2 pin unconnected to minimize leakage current. In ADC mode, input to ADC channel 2.
B4SCL/SYNCOutputI2C serial interface clock or SPI chip select input. Connect this to the IO voltage using an external pullup resistor. This pin is able to ramp up before VDD.
C1AGNDGroundGround reference point for all circuitry on the device.
C2FB0/AIN0InputVoltage feedback pin for channel 0. In voltage-output mode, connect to OUT0 for closed-loop amplifier output. In current-output mode, keep the FB0 pin unconnected to minimize leakage current. In ADC mode, input to ADC channel 0.
C3FB1/AIN1InputVoltage feedback pin for channel 1. In voltage-output mode, connect to OUT1 for closed-loop amplifier output. In current-output mode, keep the FB1 pin unconnected to minimize leakage current. In ADC mode, input to ADC channel 1.
C4A0/SDIInputAddress configuration pin for I2C or serial data input for SPI.
For A0, connect this pin to VDD, AGND, SDA, or SCL for address configuration (Section 6.5.2.2.1).
For SDI, this pin need not be pulled up or pulled down. This pin is able to ramp up before VDD.
D1CAPPowerExternal bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5μF) between CAP and AGND.
D2OUT0OutputAnalog output from DAC channel 0. Not connected in ADC mode; leave floating.
D3OUT1OutputAnalog output from DAC channel 1. Not connected in ADC mode; leave floating.
D4SDA/SCLKInput/OutputBidirectional I2C serial data bus or SPI clock input. Connect this pinto the IO voltage using an external pullup resistor in I2C mode. This pin is able to ramp up before VDD.