SLAU320AJ July 2010 – May 2021
The standard JTAG interface requires four signals for sending and receiving data. On larger MSP430 devices, these pins are dedicated for JTAG. Smaller devices with fewer total pins multiplex these JTAG lines with general-purpose functions. On these smaller devices, one additional signal is required that is used to define the state of the shared pins. This signal is applied to the TEST pin. The remaining connections required are ground and VCC when powered by the programmer. These signals are described in Table 2-3.
Pin | Direction | Description |
---|---|---|
TMS | IN | Signal to control the JTAG state machine |
TCK | IN | JTAG clock input |
TDI | IN | JTAG data input and TCLK input |
TDO | OUT | JTAG data output |
TEST | IN | Enable JTAG pins (shared JTAG devices only) |
The TEST input exists only on MSP430 devices with shared JTAG function, usually assigned to port 1. For normal operation (non-JTAG mode), this pin is internally pulled down to ground, which enables the shared pins as standard port I/O. To enable these pins for JTAG communication, refer to Section 2.3.1.1.
The TCLK signal is an input clock that must be provided to the target device from an external source. This clock is used internally as the system clock of the target device, MCLK, to load data into memory locations and to clock the CPU. There is no dedicated pin for TCLK; instead, the TDI pin is used as the TCLK input. This occurs while the MSP430 TAP controller is in the Run-Test/Idle state.
TCLK input support on the MSP430 XOUT pin exists but has been superseded by the TDI pin on all current MSP430 flash-based and FRAM-based devices. Existing FET tools, as well as the software provided with this document, implement TCLK on the TDI input pin.