SLAU320AJ July   2010  – May 2021

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 About This Document
    2. 1.2 Organization of This Document
  3. 2Programming Using the JTAG Interface
    1. 2.1 Introduction
      1. 2.1.1 MSP430 JTAG Restrictions (Noncompliance With IEEE Std 1149.1)
      2. 2.1.2 TAP Controller State Machine
    2. 2.2 Interface and Instructions
      1. 2.2.1 JTAG Interface Signals
        1. 2.2.1.1 Pros and Cons of 2-Wire Spy-Bi-Wire and 4-Wire JTAG
        2. 2.2.1.2 4-Wire JTAG Interface
        3. 2.2.1.3 2-Wire Spy-Bi-Wire (SBW) JTAG Interface
      2. 2.2.2 JTAG Access Macros
        1. 2.2.2.1 Macros for 4-Wire JTAG Interface
          1. 2.2.2.1.1 IR_SHIFT (8-Bit Instruction)
          2. 2.2.2.1.2 DR_SHIFT16 (16-Bit Data)
          3. 2.2.2.1.3 DR_SHIFT20 (20-Bit Address) (Applies Only to MSP430X Devices)
          4. 2.2.2.1.4 MsDelay (Time)
          5. 2.2.2.1.5 SetTCLK
          6. 2.2.2.1.6 ClrTCLK
        2. 2.2.2.2 Macros for Spy-Bi-Wire (SBW) Interface
      3. 2.2.3 Spy-Bi-Wire (SBW) Timing and Control
        1. 2.2.3.1 Basic Timing
        2. 2.2.3.2 TMS Slot
          1. 2.2.3.2.1 TMSH Macro
          2. 2.2.3.2.2 TMSL Macro
          3. 2.2.3.2.3 TMSLDH Macro
        3. 2.2.3.3 TDI Slot
          1. 2.2.3.3.1 TDIH Macro
          2. 2.2.3.3.2 TDIL Macro
        4. 2.2.3.4 TDO Slot
          1. 2.2.3.4.1 TDO_RD Macro
          2. 2.2.3.4.2 TDOsbw Macro (No Read)
        5. 2.2.3.5 TCLK Handling in Spy-Bi-Wire (SBW) Mode
          1. 2.2.3.5.1 SetTCLK and ClrTCLK
          2. 2.2.3.5.2 TCLK Strobes
      4. 2.2.4 JTAG Communication Instructions
        1. 2.2.4.1 Controlling the Memory Address Bus (MAB)
          1. 2.2.4.1.1 IR_ADDR_16BIT
          2. 2.2.4.1.2 IR_ADDR_CAPTURE
        2. 2.2.4.2 Controlling the Memory Data Bus (MDB)
          1. 2.2.4.2.1 IR_DATA_TO_ADDR
          2. 2.2.4.2.2 IR_DATA_16BIT
          3. 2.2.4.2.3 IR_DATA_QUICK
          4. 2.2.4.2.4 IR_BYPASS
        3. 2.2.4.3 Controlling the CPU
          1. 2.2.4.3.1 IR_CNTRL_SIG_16BIT
          2. 2.2.4.3.2 IR_CNTRL_SIG_CAPTURE
          3. 2.2.4.3.3 IR_CNTRL_SIG_RELEASE
        4. 2.2.4.4 Memory Verification by Pseudo Signature Analysis (PSA)
          1. 2.2.4.4.1 IR_DATA_PSA
          2. 2.2.4.4.2 IR_SHIFT_OUT_PSA
        5. 2.2.4.5 JTAG Access Security Fuse Programming
          1. 2.2.4.5.1 IR_PREPARE_BLOW
          2. 2.2.4.5.2 IR_EX_BLOW
    3. 2.3 Memory Programming Control Sequences
      1. 2.3.1 Start-Up
        1. 2.3.1.1 Enable JTAG Access
        2. 2.3.1.2 Fuse Check and Reset of the JTAG State Machine (TAP Controller)
      2. 2.3.2 General Device (CPU) Control Functions
        1. 2.3.2.1 Function Reference for 1xx, 2xx, 4xx Families
          1. 2.3.2.1.1 Taking the CPU Under JTAG Control
          2. 2.3.2.1.2 Set CPU to Instruction-Fetch
          3. 2.3.2.1.3 Setting the Target CPU Program Counter (PC)
          4. 2.3.2.1.4 Controlled Stop or Start of the Target CPU
          5. 2.3.2.1.5 Resetting the CPU While Under JTAG Control
          6. 2.3.2.1.6 Release Device From JTAG Control
        2. 2.3.2.2 Function Reference for 5xx and 6xx Families
          1. 2.3.2.2.1 Taking the CPU Under JTAG Control
          2. 2.3.2.2.2 Setting the Target CPU Program Counter (PC)
          3. 2.3.2.2.3 Resetting the CPU While Under JTAG Control
          4. 2.3.2.2.4 Release Device From JTAG Control
          5. 2.3.2.2.5 74
      3. 2.3.3 Accessing Non-Flash Memory Locations With JTAG
        1. 2.3.3.1 Read Access
        2. 2.3.3.2 Write Access
        3. 2.3.3.3 Quick Access of Memory Arrays
          1. 2.3.3.3.1 Flow for Quick Read (All Memory Locations)
          2. 2.3.3.3.2 Flow for Quick Write
      4. 2.3.4 Programming the Flash Memory (Using the Onboard Flash Controller)
        1. 2.3.4.1 Function Reference for 1xx, 2xx, 4xx Families
        2. 2.3.4.2 Function Reference for 5xx and 6xx Families
      5. 2.3.5 Erasing the Flash Memory (Using the Onboard Flash Controller)
        1. 2.3.5.1 Function Reference for 1xx, 2xx, 4xx Families
          1. 2.3.5.1.1 Flow to Erase a Flash Memory Segment
          2. 2.3.5.1.2 Flow to Erase the Entire Flash Address Space (Mass Erase)
        2. 2.3.5.2 Function Reference for 5xx and 6xx Families
      6. 2.3.6 Reading From Flash Memory
      7. 2.3.7 Verifying the Target Memory
      8. 2.3.8 FRAM Memory Technology
        1. 2.3.8.1 Writing and Reading FRAM
        2. 2.3.8.2 Erasing FRAM
    4. 2.4 JTAG Access Protection
      1. 2.4.1 Burning the JTAG Fuse - Function Reference for 1xx, 2xx, 4xx Families
        1. 2.4.1.1 Standard 4-Wire JTAG
          1. 2.4.1.1.1 Fuse-Programming Voltage on TDI Pin (Dedicated JTAG Pin Devices Only)
          2. 2.4.1.1.2 Fuse-Programming Voltage On TEST Pin
        2. 2.4.1.2 Fuse-Programming Voltage Using SBW
      2. 2.4.2 Programming the JTAG Lock Key - Function Reference for 5xx, 6xx, and FRxx Families
        1. 2.4.2.1 Flash Memory Devices
        2. 2.4.2.2 FRAM Memory Devices
      3. 2.4.3 Testing for a Successfully Protected Device
      4. 2.4.4 Unlocking an FRAM Device in Protected and Secured Modes
        1. 2.4.4.1 FR5xx and FR6xx Devices
        2. 2.4.4.2 FR4xx and FR2xx Devices
      5. 2.4.5 Memory Protection Unit Handling
      6. 2.4.6 Intellectual Property Encapsulation (IPE)
      7. 2.4.7 FRAM Write Protection
    5. 2.5 JTAG Function Prototypes
      1. 2.5.1 Low-Level JTAG Functions
      2. 2.5.2 High-Level JTAG Routines
    6. 2.6 JTAG Features Across Device Families
    7. 2.7 References
  4. 3JTAG Programming Hardware and Software Implementation
    1. 3.1 Implementation History
    2. 3.2 Implementation Overview
    3. 3.3 Software Operation
    4. 3.4 Software Structure
      1. 3.4.1 Programmer Firmware
      2. 3.4.2 Target Code
        1. 3.4.2.1 Target Code Download for Replicator430, Replicator430X, and Replicator430Xv2
        2. 3.4.2.2 Target Code Download for Replicator430FR (FRAM)
    5. 3.5 Hardware Setup
      1. 3.5.1 Host Controller
      2. 3.5.2 Target Connection
      3. 3.5.3 Host Controller or Programmer Power Supply
      4. 3.5.4 Third-Party Support
  5. 4Errata and Revision Information
    1. 4.1 Known Issues
    2. 4.2 Revisions and Errata From Previous Documents
  6. 5Revision History

3.4.1 Programmer Firmware

The programming software is partitioned in three levels and consists of nine files in addition to the target program (see Table 3-1).

Table 3-1 Programmer Firmware
Top level Specifies which programming functions (erase, program, verify, blow fuse) are to be executed.
Replicator430.c
Replicator430X.c
Replicator430Xv2.c
Replicator430FR.c		 Contains the main section, which can be modified to meet custom requirements. In the main section of this program, the target device is erased, checked for successful erasure, and programmed. Programming loads the provided example code to the target device's memory space. (The provided code file simply flashes port pins P1.0 and/or P5.1, which drive the LEDs on the socket board provided with the FET tools, available from Texas Instruments MSP430 Group. This is the compiled FETXXX_1.s43 example code file.) This file must be replaced by the required user program and added to the project to be compiled and loaded into the host. To demonstrate the capabilities of the MSP430 JTAG interface, additional code is included, which manipulates the I/O-ports and RAM of the target device. These routines can be used to test the target device and PCB for successful communication.
Config430.h
Config430X.h
Config430Xv2.h
Config430FR.h		 Contains high-level definitions to be set by the user before initially programming the host controller firmware. These so called 'quick start options' specify among other things the voltage level supplied by the Replicator hardware and the interface used to communicate with the target device.
Target_Code.h Contains the basic declarations of the program code of the target device. If a C-header file should be implemented to program the target device instead of an assembly file, replace the content of Target_Code.h by the output of srec_cat.exe and remove Target_Code.s43 (IAR) or Target_Code.asm (CCS) from the project. The Target_Code.h file is generated by the srec_cat.exe file directly or by the srec.bat file.
JTAG functions All MSP430-specific functions are defined here. These files should not be modified under any circumstance.
JTAGfunc.c
JTAGfunc430X.c
JTAGfunc430Xv2.c
JTAGfunc430FR.c		 Contain the MSP430-specific functions needed for flash programming
JTAGfunc.h
JTAGfunc430X.h
JTAGfunc430Xv2.h
JTAGfunc430FR.h		 Contain constant definitions and function prototypes used for JTAG communication
JSBW.c Contains special functions that emulate the Spy-Bi-Wire interface to wake up MSP430 devices from LPMx.5 (Replicator430Xv2 and Replicator430FR only)
Low-level functions All functions that depend specifically on the host controller (JTAG port I/O and timing functions) are located here. These files need to be adapted if a host controller other than the MSP430F5437 is implemented.
LowLevelFunc430.c
LowLevelFunc430X.c
LowLevelFunc430Xv2.c		 Contain the basic host-specific functions
LowLevelFunc430.h
LowLevelFunc430X.h
LowLevelFunc430Xv2.h		 Contain host-specific definitions and function prototypes
Devices Describes features and differences between MSP430 devices with respect to FLASH programming. (Replicator430 and Replicator430X only)
Devices430.c
Devices430x.c		 Functions to distinguish MSP430 devices concerning FLASH programming.
Devices430.h
Devices430x.h		 Device function prototypes and definitions for FLASH programming.
Funclets Contain target code which is written into the target's RAM to speed up writing to and erasing from the device's NVM. (These files can only be rebuilt using IAR Embedded Workbench and SRecord)
FlashErase.c
FlashWrite.c		 Funclets to speed up flash erase and programming
FramErase.c
FramWrite.c		 Funclets to speed up FRAM erase and programming