SLAU320AJ July 2010 – May 2021
As shown in Figure 2-8, the TDO operation is allocated one time slot (see also the detailed timing shown in Figure 2-10). The master should release control of the SBWTDIO line based off of the rising edge of SBWTCK of the TDI cycle. After the master releases the SBWTDIO line, an internal bus keeper holds the voltage on the line. The next falling edge of SBWTCK triggers the slave to start driving the bus. The slave only drives the SBWTDIO line during the low time of the SBWTCK cycle. The master should not enable its drivers until the slave has released the SBWTDIO line. Therefore, the master could use the rising edge of the SBWTCK signal as a trigger point to enable its driver.
The low phase of the clock signal supplied on SBWTCK must not be longer than 7 µs. If the low phase is longer, the SBW logic is deactivated, and it must be activated again according to Section 2.3.1.
When using the provided source code example, make sure that interrupts are disabled during the SBWTCK low phase to ensure accurate timings.
The following macros are located in the LowLevelFunc header file in the Replicator example project.