SLAU640B April   2019  – March 2023

 

  1.   Introduction
  2. 1Trademarks
  3. 2Equipment
    1. 2.1 Evaluation Board Feature Identification Summary
    2. 2.2 Required Equipment
  4. 3Setup Procedure
    1. 3.1  Install the High Speed Data Converter (HSDC) Pro Software
    2. 3.2  Install the Configuration GUI Software
    3. 3.3  Connect the EVM and TSW14J57EVM
    4. 3.4  Connect the Power Supplies to the Boards (Power Off)
    5. 3.5  Connect the Signal Generators to the EVM (RF Outputs Disabled Until Directed)
    6. 3.6  Turn On the TSW14J57EVM Power and Connect to the PC
    7. 3.7  Turn On the ADC12DJ5200RFEVM/SEEVM Power Supplies and Connect to the PC
    8. 3.8  Turn On the Signal Generator RF Outputs
    9. 3.9  Open the ADC12DJ5200RFEVM/SEEVM GUI and Program the ADC and Clocks
    10. 3.10 Calibrate the ADC Device on the EVM
    11. 3.11 Open the HSDC Software and Load the FPGA Image to the TSW14J57EVM
    12. 3.12 Capture Data Using the HSDC Pro Software
  5. 4Device Configuration
    1. 4.1 Supported JESD204C Device Features
    2. 4.2 Tab Organization
    3. 4.3 Low-Level Control
  6. 5Troubleshooting the ADC12DJ5200RFEVM/SEEVM
  7. 6References
    1. 6.1 Technical Reference Documents
    2. 6.2 TSW14J57EVM Operation
  8. 7HSDC Pro Settings for Optional ADC Device Configuration
    1. 7.1 Changing the Number of Frames per Multi-Frame (K)
    2. 7.2 Customizing the EVM for Optional Clocking Support
      1. 7.2.1 External Clocking Option (Default)
      2. 7.2.2 Onboard Clocking Option
      3. 7.2.3 External Reference Clocking Option
  9. 8Signal Routing
    1. 8.1 Signal Routing
  10.   A Analog Inputs
  11.   B Jumpers and LEDs
    1. 10.1 Jumper settings
  12.   B Revision History

4.1 Supported JESD204C Device Features

The ADC device supports some configuration of the JESD204C interface. Due to limitations in the TSW14J57EVM firmware, all JESD204C link features of the ADC device are not supported. #GUID-3D36C068-0F57-4802-BE16-948618ED2BFA/SLAU7013602 lists the supported and non-supported features.

Table 4-1 Supported and Non-Supported Features of the JESD204C Device
JESD204C FeatureSupported by ADC DeviceSupported by TSW14J57EVMSupported by TSW14J58EVM
Number of lanes per link (L)L = 1, 2, 3, 4, 6, 8(1)L = 1, 2, 3, 4, 6, 8 supportedL = 1, 2, 3, 4, 6, 8 supported
Total number of lanes active2, 4, 6, 8, 12, 162, 4, 6, 8, 12, 162, 4, 6, 8, 12, 16
Number of frames per multiframe (K)Kmin = 3–256,(1)
Kmax = 256, Kstep = 1 or 2		Most values of K supported, constrained by requirement that
K × F = 4n		Most values of K supported, constrained by requirement that
K × F = 4n
ScramblingSupportedSupportedSupported
Test patternsPRBS7, PRBS9, PRBS15, PBRS23, PRBS31, Ramp, Transport Layer test, D21.5, K28.5, Repeat ILA, Modified RPAT, Serial Out 0, Serial Out 1, Clock test, ADC Test Pattern(1)ILA, Ramp, Long/Short TransportILA, Ramp, Long/Short Transport
SpeedLane rates from 0.8 to 17.12 Gbps(1)Lane rates from 2 to 15 Gbps
ƒ(SAMPLE) parameter must be properly set in HSDC Pro GUI.		Lane rates from 0.6 to 17.16Gbps
ƒ(SAMPLE) parameter must be properly set in HSDC Pro GUI.
(1) Dependent on bypass or decimation mode and output rate selection. Always disable the JESD204 block before changing any of the JESD204C settings. Once the settings are changed, re-enable the JESD204 block.