SLAZ742E July   2023  – December 2025 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1

 

  1.   1
  2.   Abstract
  3. 1Functional Advisories
  4. 2Preprogrammed Software Advisories
  5. 3Debug Only Advisories
  6. 4Fixed by Compiler Advisories
  7. 5Device Nomenclature
  8. 6Advisory Descriptions
    1. 6.1  ADC_ERR_01
    2. 6.2  ADC_ERR_02
    3. 6.3  ADC_ERR_05
    4. 6.4  ADC_ERR_06
    5. 6.5  BSL_ERR_01
    6. 6.6  COMP_ERR_02
    7. 6.7  COMP_ERR_03
    8. 6.8  CLK_ERR_01
    9. 6.9  CPU_ERR_01
    10. 6.10 CPU_ERR_02
    11. 6.11 CPU_ERR_03
    12. 6.12 DMA_ERR_01
    13. 6.13 FLASH_ERR_02
    14. 6.14 FLASH_ERR_04
    15. 6.15 FLASH_ERR_05
    16. 6.16 FLASH_ERR_06
    17. 6.17 FLASH_ERR_08
    18. 6.18 GPIO_ERR_01
    19. 6.19 GPIO_ERR_03
    20. 6.20 GPIO_ERR_04
    21. 6.21 I2C_ERR_01
    22. 6.22 I2C_ERR_02
    23. 6.23 I2C_ERR_03
    24. 6.24 I2C_ERR_04
    25. 6.25 I2C_ERR_05
    26. 6.26 I2C_ERR_06
    27. 6.27 I2C_ERR_07
    28. 6.28 I2C_ERR_08
    29. 6.29 I2C_ERR_09
    30. 6.30 I2C_ERR_10
    31. 6.31 I2C_ERR_13
    32. 6.32 MATHACL_ERR_01
    33. 6.33 MATHACL_ERR_02
    34. 6.34 PMCU_ERR_06
    35. 6.35 PMCU_ERR_08
    36. 6.36 PMCU_ERR_10
    37. 6.37 PWREN_ERR_01
    38. 6.38 RST_ERR_01
    39. 6.39 RTC_ERR_01
    40. 6.40 SPI_ERR_01
    41. 6.41 SPI_ERR_02
    42. 6.42 SPI_ERR_03
    43. 6.43 SPI_ERR_04
    44. 6.44 SPI_ERR_05
    45. 6.45 SPI_ERR_06
    46. 6.46 SPI_ERR_07
    47. 6.47 SRAM_ERR_02
    48. 6.48 SYSCTL_ERR_02
    49. 6.49 SYSCTL_ERR_03
    50. 6.50 SYSCTL_ERR_04
    51. 6.51 SYSOSC_ERR_01
    52. 6.52 SYSOSC_ERR_02
    53. 6.53 SYSOSC_ERR_04
    54. 6.54 SYSPLL_ERR_01
    55. 6.55 TIMER_ERR_01
    56. 6.56 TIMER_ERR_04
    57. 6.57 TIMER_ERR_06
    58. 6.58 TIMER_ERR_07
    59. 6.59 UART_ERR_01
    60. 6.60 UART_ERR_02
    61. 6.61 UART_ERR_04
    62. 6.62 UART_ERR_05
    63. 6.63 UART_ERR_06
    64. 6.64 UART_ERR_07
    65. 6.65 UART_ERR_08
    66. 6.66 UART_ERR_09
    67. 6.67 UART_ERR_10
    68. 6.68 UART_ERR_11
    69. 6.69 VREF_ERR_01
    70. 6.70 VREF_ERR_02
    71. 6.71 WWDT_ERR_01
    72. 6.72 WWDT_ERR_02
  9.   Trademarks
  10. 7Revision History

6.42 SPI_ERR_03

SPI Module

Category

Functional

Function

When configured as peripheral, enable CSCLR will result in the received data will have a right shift in SPH=0 mode

Description

When enabled CSCLR in peripheral mode, if there has glitch on SCK line when CS is active or inactive, the received data will have 1-bit right shift in the next first frame. This issue is seen in Motorola SPI Frame Format with SPH=0, and will impact multi-peripheral mode which has the case that SCK toggle during CS inactive.

Workaround

1. Set CSCLR=0h.
2. Always drop the first frame when set CSCLR=1h in SPH=0 mode.