SLAZ763 July   2025 MSPM0H3216

 

  1.   1
  2.   Abstract
  3. 1Functional Advisories
  4. 2Preprogrammed Software Advisories
  5. 3Debug Only Advisories
  6. 4Fixed by Compiler Advisories
  7. 5Device Nomenclature
    1. 5.1 Device Symbolization and Revision Identification
  8. 6Advisory Descriptions
    1. 6.1  ADC_ERR_05
    2. 6.2  CPU_ERR_02
    3. 6.3  CPU_ERR_03
    4. 6.4  FLASH_ERR_02
    5. 6.5  FLASH_ERR_03
    6. 6.6  I2C_ERR_04
    7. 6.7  I2C_ERR_05
    8. 6.8  I2C_ERR_06
    9. 6.9  I2C_ERR_07
    10. 6.10 I2C_ERR_08
    11. 6.11 I2C_ERR_09
    12. 6.12 I2C_ERR_10
    13. 6.13 LFXT_ERR_03
    14. 6.14 LFXT_ERR_04
    15. 6.15 PMCU_ERR_13
    16. 6.16 RST_ERR_01
    17. 6.17 SPI_ERR_04
    18. 6.18 SPI_ERR_05
    19. 6.19 SPI_ERR_06
    20. 6.20 SPI_ERR_07
    21. 6.21 SWD_ERR_01
    22. 6.22 SYSOSC_ERR_02
    23. 6.23 TIMER_ERR_04
    24. 6.24 TIMER_ERR_06
    25. 6.25 UART_ERR_01
    26. 6.26 UART_ERR_02
    27. 6.27 UART_ERR_04
    28. 6.28 UART_ERR_05
    29. 6.29 UART_ERR_06
    30. 6.30 UART_ERR_07
    31. 6.31 UART_ERR_08
  9. 7Trademarks
  10. 8Revision History

6.19 SPI_ERR_06

SPI Module

Category

Functional

Function

IDLE/BUSY status does not reflect the correct status of SPI IP when debug halt is asserted

Description

IDLE/BUSY is independent of halt, it is only gating the RXFIFO/TXFIFO writing/reading strobes. So, if controller is sending data, although it's not latched in FIFO but the BUSY is getting set. The POCI line transmits the previously transmitted data on the line during halt

Workaround

Don't use IDLE/BUSY status when SPI IP is halted.