SLLA685 July   2026 TCAN4550-Q1 , TCAN4551-Q1

 

  1.   1
  2.   Abstract
  3. 1Basic Introduction to TCAN455x-Q1
    1. 1.1 What is an SBC?
    2. 1.2 What is CAN FD?
    3. 1.3 What are the advantages of the TCAN455x-Q1?
    4. 1.4 Difference between TCAN4550-Q1 and TCAN4551-Q1
  4. 2TCAN455x-Q1 Peripheral Circuit Design
    1. 2.1 Power Supply Pins
    2. 2.2 SPI and IO Pins
    3. 2.3 CAN Pins
    4. 2.4 Clock Pins
    5. 2.5 Other Pins
  5. 3Clock Circuit Design for the TCAN455x-Q1
    1. 3.1 Internal Clock Circuit and Operating Principles
    2. 3.2 Quartz Crystal Clock Mode Principle
    3. 3.3 Quartz Crystal Parameters
    4. 3.4 Quartz Crystal Selection
      1. 3.4.1 Issue of Erroneous Entry into Single-Ended Clock Mode
      2. 3.4.2 Solutions for Erroneous Entry into Single-Ended Clock Mode
  6. 4Conclusion
  7. 5References

3.3 Quartz Crystal Parameters

The design goals for the quartz crystal oscillator circuit include:

  1. Ensuring the crystal and external circuitry meet oscillation conditions. This requires a sufficiently large negative resistance –Rneg to effectively "cancel" the crystal's positive resistance, allowing the crystal to start and maintain oscillation.
    • It is generally recommended that the negative resistance |–Rneg| be 3–5 times the load resistance RLoad.
    • If the –Rneg margin is low and RLoad is too high, safe crystal operation cannot be guaranteed. This may require adjusting the load capacitance CLoad by increasing external capacitors CL1 and CL2 to reduce the total load resistance RLoad. However, capacitor adjustments may shift the crystal frequency, so the oscillation frequency should be measured to ensure it remains within specification.
  2. Avoiding overdriving the crystal and controlling crystal power dissipation. Excessive drive level DL can reduce lifetime, accelerate aging, cause mechanical damage, and generate spurious or harmonic responses.
    • Crystal manufacturers typically specify a maximum DL that must not be exceeded.
    • Excessive DL may cause the OSC2 oscillation amplitude to increase and approach GND, potentially causing the TCAN455x to erroneously enter single-ended clock mode (see Section 3.4.1). To avoid this, it is recommended to add a damping resistor Rd to reduce DL.
  3. Minimizing crystal frequency deviation.
    • Crystal manufacturers typically specify the load capacitance CLoad required to achieve the stated frequency accuracy. If CLoad is too small, the actual frequency may be higher than the target; conversely, if CLoad is too large, the frequency may be lower.

Therefore, during design, customers must balance the trade-offs among –Rneg, DL, and f performance to determine the appropriate crystal and external component selection.