SLLSFX1B September   2024  – February 2025 ISO6163

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics—5V Supply (±10%)
    10. 5.10 Supply Current Characteristics—5V Supply (±10%)
    11. 5.11 Electrical Characteristics—3.3V Supply (±10%)
    12. 5.12 Supply Current Characteristics—3.3V Supply (±10%)
    13. 5.13 Electrical Characteristics—2.5V Supply (Minimum)
    14. 5.14 Supply Current Characteristics—2.5V Supply  (Minimum)
    15. 5.15 Switching Characteristics—5V Supply (±10%)
    16. 5.16 Switching Characteristics—3.3V Supply (±10%)
    17. 5.17 Switching Characteristics—2.5V Supply (Minimum)
    18. 5.18 Insulation Characteristics Curves
    19. 5.19 Typical Characteristics
      1. 5.19.1 Typical Characteristics: Supply Current ACTIVE state
      2. 5.19.2 Typical Characteristics: High-Speed Channels (ACTIVE state)
      3. 5.19.3 Typical Characteristics: Supply Current STANDBY State
      4. 5.19.4 Typical Characteristics: Low-Speed Control Channels (ACTIVE and STANDBY States)
      5. 5.19.5 Typical Characteristics: Undervoltage Threshold
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Functional Block Diagram
      2. 7.1.2 Feature Description
    2. 7.2 High-Speed Data Channels: A, B, E and F
    3. 7.3 Low-Speed Control Channels With Automatic Enable: C and D
      1. 7.3.1 Low-Speed Control Channels: Timing and Level Details for Automatic Enable
      2. 7.3.2 Low-Speed Control Channels: Considerations if Used for Data
      3. 7.3.3 Low-Speed Control Channels: Considerations During Power Up and Device Reset Events
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device I/O Schematics
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 PCB Material
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
16-DW
IEC 60664-1
CLR External clearance(1) Side 1 to side 2 distance through air >8 mm
CPG External creepage(1) Side 1 to side 2 distance across package surface >8 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm
CTI Comparative tracking index IEC 60112 >600 V
Material Group According to IEC 60664-1 I
Overvoltage category Rated mains voltage ≤ 600VRMS I-IV
Rated mains voltage ≤ 1000VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1060 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test. 750 VRMS
DC voltage 1060 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60s (qualification);
VTEST = 1.2 x VIOTM, t= 1s (100% production)		 7071 VPK
VIMP Maximum impulse voltage(3) Tested in air, 1.2/50µs waveform per IEC 62368-1 8000 VPK
VIOSM Maximum surge isolation voltage(4) VIOSM ≥ 1.3 x VIMP; Tested in oil (qualification test),
1.2/50μs waveform per IEC 62368-1		 10400 VPK
qpd Apparent charge(5) Method a, After Input-output safety test subgroup 2/3,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 x VIORM, tm = 10s		 ≤5 pC
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.6 x VIORM, tm = 10s		 ≤5
Method b: At routine test (100% production);
Vini = 1.2 x VIOTM, tini = 1s;
Vpd(m) = 1.875 x VIORM, tm = 1s (method b1) or 
Vpd(m) = Vini, tm = tini (method b2)		 ≤5
CIO Barrier capacitance, input to output(6) VIO = 0.4 × sin (2 πft), f = 1MHz ≅2.4 pF
RIO Insulation resistance, input to output(6) VIO = 500V,  TA = 25°C >1012 Ω
VIO = 500V,  100°C ≤ TA ≤ 125°C >1011
VIO = 500V at  TS = 150°C >109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO , t = 60s (qualification); VTEST = 1.2 × VISO , t = 1s (100% production) 5000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier tied together creating a two-pin device.