SLLSFX4A February   2025  – February 2025 TCAN857-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings, IEC Specification
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Characteristics
    6. 5.6  Power Supply Characteristics
    7. 5.7  Dissipation Ratings
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pin Description
        1. 7.3.1.1 TXD
        2. 7.3.1.2 GND
        3. 7.3.1.3 VCC
        4. 7.3.1.4 RXD
        5. 7.3.1.5 VIO
        6. 7.3.1.6 CANH and CANL
        7. 7.3.1.7 S (Silent)
      2. 7.3.2 CAN Bus States
      3. 7.3.3 TXD Dominant Timeout (DTO)
      4. 7.3.4 CAN Bus Short-circuit Current Limiting
      5. 7.3.5 Thermal Shutdown (TSD)
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 Unpowered Device
      8. 7.3.8 Floating pins
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 Normal Mode
      3. 7.4.3 Silent Mode
      4. 7.4.4 Driver and Receiver Function
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 CAN Termination
      2. 8.2.2 Detailed Design Procedures
        1. 8.2.2.1 Bus Loading, Length and Number of Nodes
      3. 8.2.3 System Examples
      4. 8.2.4 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.9 Switching Characteristics

Over recommended operating conditions with TA = -40℃ to 125℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Device Switching Characteristics
tPROP(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant Normal mode, VIO = 3V to 5V, RL = 60Ω, CL = 100pF, CL_RXD = 15pF    100 220 ns
tPROP(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive Normal mode, VIO = 3V to 5V, RL = 60Ω, CL = 100pF, CL_RXD = 15pF    110 220 ns
tMODE Mode change time, from Normal to Silent or from Silent to Normal 45 µs
tWK_FILTER Filter time for a valid wake-up pattern 0.5 1.8 µs
tWK_TIMEOUT Bus wake-up timeout value 0.8 6 ms
Driver Switching Characteristics
tpHR Propagation delay time, high TXD to driver recessive (dominant to recessive) RL = 60Ω, CL = 100pF, RCM = open 50 ns
tpLD Propagation delay time, low TXD to driver dominant (recessive to dominant) 45 ns
tsk(p) Pulse skew (|tpHR - tpLD|) 4 ns
tR Differential output signal rise time 32 ns
tF Differential output signal fall time 27 ns
tTXD_DTO Dominant timeout RL = 60Ω, CL = 100pF 0.8 6.5 ms
Receiver Switching Characteristics
tpRH Propagation delay time, bus recessive input to high output (dominant to recessive) CL_RXD = 15pF 75 ns
tpDL Propagation delay time, bus dominant input to low output (recessive to dominant) 70 ns
tR RXD output signal rise time 10 ns
tF RXD output signal fall time 10 ns
FD Timing Characteristics
tΔBit(Bus) Transmitted recessive bit width variation:  tBIT(TXD) = 500 ns RL = 60Ω, CL = 100pF, CL_RXD = 15pF
tΔBit(Bus) = tBIT(Bus) - tBIT(TXD)		 -65 30 ns
tΔBit(Bus) Transmitted recessive bit width variation:  tBIT(TXD) = 200 ns RL = 60Ω, CL = 100pF, CL_RXD = 15pF
tΔBit(Bus) = tBIT(Bus) - tBIT(TXD)		 -45 10 ns
tΔBit(RXD) Received recessive bit width variation: tBIT(TXD) = 500 ns RL = 60Ω, CL = 100pF, CL_RXD = 15pF
tΔBit(Bus) = tBIT(RXD) - tBIT(TXD)		 -100 50 ns
tΔBit(RXD) Received recessive bit width variation: tBIT(TXD) = 200 ns RL = 60Ω, CL = 100pF, CL_RXD = 15pF
tΔBit(Bus) = tBIT(RXD) - tBIT(TXD)		 -80 20 ns
tΔREC Receiver timing symmetry with tBIT(TXD) = 500 ns RL = 60Ω, CL = 100pF, CL_RXD = 15pF
ΔtREC = tBIT(RXD) - tBIT(BUS)		 -65 40 ns
tΔREC Receiver timing symmetry with tBIT(TXD) = 200 ns -45 15 ns