SLLSG02A February   2026  – March 2026 ISOW3080 , ISOW3086

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Supply Current Characteristics at VISOOUT = 3.3 V (ISOW308x)
    11. 6.11 Supply Current Characteristics at VISOOUT = 5 V (ISOW308xP)
    12. 6.12 Switching Characteristics at VISOOUT = 3.3 V (ISOW308x)
    13. 6.13 Switching Characteristics at VISOOUT = 5 V (ISOW308xP)
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Power Isolation
    3. 8.3 Signal Isolation
    4. 8.4 RS-485
    5. 8.5 Functional Block Diagram
    6. 8.6 Feature Description
      1. 8.6.1 Power-Up and Power-Down Behavior
      2. 8.6.2 Protection Features
      3. 8.6.3 Failsafe Receiver
      4. 8.6.4 Glitch-Free Power Up and Power Down
    7. 8.7 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Data Rate, Bus Length and Bus Loading
        2. 9.2.2.2 Stub Length
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 12.1 Tape and Reel Information

8.7 Device Functional Modes

Table 8-1 lists the supply configuration for these devices:

Table 8-1 Supply Configuration Function Table
INPUTSOUTPUT
VDD(1)VDDLVISOOUTSection 6.3
< VDD(UVLO+)>VDDL(UVLO+)OFF
>VDD(UVLO+)<VDDL(UVLO+)ON
(1) VDD= 3.3V for Profibus devices (ISOW3080P and ISOW3086P) is an invalid operation and is not supported

Table 8-2 shows the driver functional modes:

Table 8-2 Driver Functional Table
INPUTSOUTPUTS
VDD(1)VDDLD DEY, AZ, B
PUPUHHHL
LHLH
XLHi-ZHi-Z
XOpenHi-ZHi-Z
OpenHHL
PDPUXXHi-ZHi-Z
PUPD(2)XXInvalid Operation
(1) PU=Powered up, PD=Powered down; H=high level; L=Low level; X=Irrelevant; Hi-Z=High impedance state
(2) A strongly driven input signal on D, DE or RE can weakly power the floating VDDL through an internal protection diode and cause an undetermined output.

When the driver enable pin, DE, is logic high, the differential outputs, Y and Z, follow the logic states at data input, D. A logic high at the D input causes the Y output to go high and the Z output to go low. Therefore the differential output voltage defined by Equation 1 is positive.

Equation 1. VOD = VY – VZ

A logic low at the D input causes the Z output to go high and the Y output to go low. Therefore the differential output voltage defined by Equation 1 is negative. A logic low at the DE input causes both outputs to go to the high-impedance (Hi-Z) state. The logic state at the D pin is irrelevant when the DE input is logic low. The DE pin has an internal pulldown resistor to ground. The driver is disabled (bus outputs are in the Hi-Z) by default when the DE pin is left open. The D pin has an internal pullup resistor. The Y output goes high and the Z output goes low when the D pin is left open while the driver enabled.

Table 8-3 shows the receiver functional modes:

Table 8-3 Receiver Functional Table
INPUTSOUTPUT
VDD(1)VDDLDifferential Input VID = VA- VBRER
PUPUVID > VIT+LH
VIT- < VID < VIT+LIndeterminate
VID < VIT-LL
XHHi-Z
XOpenHi-Z
Open, Short, IdleLH
PDPUXXHi-Z
PUPD(2)XXInvalid Operation
(1) PU=Powered up, PD=Powered down; H=high level; L=Low level; X=Irrelevant; Hi-Z=High impedance state
(2) A strongly driven input signal on D, DE or RE can weakly power the floating VDDL through an internal protection diode and cause an undetermined output.

The receiver is enabled when the receiver enable pin, RE, is logic low. The receiver output, R, goes high when the differential input voltage defined by Equation 2 is greater than the positive input threshold, VTH+.

Equation 2. VID = VA – VB

The receiver output, R, goes low when the differential input voltage defined by Equation 2 is less than the negative input threshold, VTH– . If the VID voltage is between the VTH+ and VTH– thresholds, the output is indeterminate. The receiver output is in the Hi-Z state and the magnitude and polarity of VID are irrelevant when the RE pin is logic high or left open. The internal biasing of the receiver inputs causes the output to go to a failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).