SLLU397 April   2025 TCAN1043-Q1 , TCAN1043G-Q1 , TCAN1043H-Q1 , TCAN1043HG-Q1 , TCAN1043N-Q1 , TCAN1144-Q1 , TCAN1145-Q1 , TCAN1146-Q1 , TCAN1463-Q1 , TCAN1473-Q1 , TCAN1473A-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1.     Jumper Information
    2. 2.1 EVM Setup and Operation
      1. 2.1.1 Overview and Basic Operation Settings
        1. 2.1.1.1  Power Supply Inputs VBAT, VCC and VIO
        2. 2.1.1.2  I/O Headers (J2, J4)
        3. 2.1.1.3  Pin 14
        4. 2.1.1.4  TXD Input
        5. 2.1.1.5  RXD Output
        6. 2.1.1.6  Pin 11
        7. 2.1.1.7  Pin 6
        8. 2.1.1.8  Pin 8
        9. 2.1.1.9  Pin 7
        10. 2.1.1.10 WAKE Pin
        11. 2.1.1.11 SIC Network Configuration (J10 and J11)
      2. 2.1.2 Using CAN Bus Load, Termination, and Protection Configurations
      3. 2.1.3 Using Customer Installable I/O Options for Current Limiting, Pullup and Pulldown, Noise Filtering
  7. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  8. 4Additional Information
    1. 4.1 Trademarks

2.1.1.8 Pin 8

Pin 8 of the transceiver is normally a status indicator flag (nFAULT) or a SPI clock pin (SCLK). The signal path to the J2 header is pre-installed with a 100 nF filtering capacitor, C15. An optional pulldown resistor to GND can be installed on R21, and an optional pullup resistor to VIO can be installed on R19. Additionally, diode D2 signifies whether pin 8 is high or low. Note that the diode is inverted.