Resolver secondary windings operate unloaded. For this reason, the resolver primary (excitation) coil appears mainly as an inductor. Inductors and capacitors cannot dissipate any power. For this reason, the resolver excitation operates with power factor close to zero, drawing only reactive power. The reactive power heats up the source – the amplifier.

There are multiple ways to analyze the power stage:

• Considering power factor
• Analyzing impedance network
• Frequency domain analysis, but all result in the same outcome.

Figure 4-2 Class-D Power Stage Analysis

Figure 4-2 – Circuit A simplifies the power stage for the analysis. Capacitors C10, C17 are significantly smaller value and we can ignore them for the analysis. Additionally, the power stage is symmetrical therefore inductor values L2, L3 and capacitor values C9, C16 are same. Voltage sources V_OUTP and V_OUTN are always positive with reference to ground. This effectively doubles the voltage seen by the resolver. Figure 4-2 – Circuit B further simplifies the circuit for the analysis. The series combination of output capacitors C9 and C16 and the resolver winding form a parallel resonant circuit (tank).

Understanding the concept of a parallel resonant tank in the context of resolver excitation is important. At the resonant frequency, the current through the capacitor cancels out the current through the inductor. The impedance of the resonant circuit becomes infinite and the current supplying the resonant tank drops to zero. Using the resonance is beneficial in the resolver applications as the excitation frequency remains constant. By careful selection of the parallel capacitor, engineers can reduce the power consumption of the resolver excitation amplifier and significantly improve thermals. Figure 4-3 shows the impedance plot for the circuit example in Figure 4-4. The resonant peak occurs at 6.9kHz where the impedance increases to 144Ω. At the nominal excitation frequency f_EXC=10kHz the impedance is 57Ω.

Figure 4-3 Impedance Plot for the Parallel Resonant Tank

Figure 4-4 Parallel Resonant Tank Simulation Circuit (QSPICE)

The parallel capacitance is set the way the resonance occurs at excitation frequency. However, there are additional considerations. The value tolerance moves the resonant frequency up and down. Additionally, multi-layer ceramic capacitors (MLCC) have DC bias derating. The output capacitance of the power stage also defines the output ripple. Reducing the capacitance increases the output ripple. To maintain the output ripple, the inductance of L2, L3 has to be proportionally higher. Higher inductance decreases ripple current through the power stage and maintains similar cut-off frequency as the circuit in device data sheet. Current values of inductors L2, L3 and capacitors C9, C16 are the result of a good compromise between the output ripple, cut-off frequency and the inductor size. The resonant peak at approximately 6.9kHz is right in the middle of the desired excitation frequency range from 5 to 10kHz.