SLOA338 March   2025 TSD5402-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction TO RESOLVER and LVDT sensors
  5. 2Conventional Excitation Amplifier
  6. 3Excitation Amplifier Using Class-D Amplifiers
  7. 4Class-D Resolver Excitation Design Details
    1. 4.1 Components Selection for the Power Stage
    2. 4.2 Input Filter Components Selection
  8. 5Practical Experiments
    1. 5.1 Test Setup
    2. 5.2 Output Waveforms for Default Conditions
    3. 5.3 Amplifier Transfer Function
    4. 5.4 Using PWM for Generating the Reference Signal
    5. 5.5 Thermal Image and Comparison Against the Linear Design
    6. 5.6 Output Spectrum
    7. 5.7 Total Harmonic Distortion (THD)
    8. 5.8 Fail Events
  9. 6Summary
  10. 7References

4 Class-D Resolver Excitation Design Details

Table 4-1 lists input design parameters for the excitation amplifier.

Table 4-1 Excitation Amp Input Parameters
ParameterValueUnit
Excitation frequency5 to 10kHz
Excitation voltage4 to 7VRMS
Resolver excitation winding inductance at 10kHz1.05mH
Resolver excitation winding equivalent series resistance14.42Ω
Input voltage range9-18V
TSD5402-Q1 Resolver Excitation Amplifier SchematicFigure 4-1 TSD5402-Q1 Resolver Excitation Amplifier Schematic

Figure 4-1 shows more detailed circuit diagram of the Class-D excitation amplifier. This circuit diagram is identical to the tested board except a few parts missing (LED, LDO). Capacitors C1 through C4 and inductor L1 form an input PI filter. This filter reduces switching noise spreading to the rest of the system. In most situations the filter is not necessary as the amplifier connects to a noisy DC/DC converter anyways. Resistors R8, R9, and R12 are pull-up resistors for the optional I­2C­ bus and the FAULT signal. The input reference signal from the generator AFG enters the low-pass filter R2, C11. Amplifier input pins IN_P, IN_N use capacitors C7, C15 for AC-coupling. The resolver application uses single-ended input. For this reason, the other leg of the capacitor C15 connects to the ground. Resistors R13, R11 set the default configuration for Hi-Z and STANDBY input pins. The capacitor C19 is a bypass capacitor for the integrated voltage regulator. The power stage is symmetrical for both outputs. Capacitors C8, C13 are bootstrap capacitors that allow for internal biasing of the power stage. Resistors R3, R7, and capacitors C12, C18 form two snubber circuits that reduce inductive ringing at switch nodes. Snubber component values are different for each design and are the result of laboratory experiments. Components selection for the ouptut filter is critical. The output LC filter L2 (L3), C9 (C16), C10 (C17) values are different to the data sheet recommendation. This resolver design implements 47uH inductor and 1uF capacitor values. This combination sets the cut-off frequency to 23.2kHz. The main reason for this change is reducing the power dissipation by adjusting the overall load impedance.