SLUA560D June 2011 – March 2022 UCC28950 , UCC28950-Q1 , UCC28951 , UCC28951-Q1

9 Select FETs QE and QF

The synchronous FETs are chosen based on current and voltage ratings; as well as, power dissipation to meet the designs efficiency goals. This can be a trial an error process. We selected an evaluated a 75-V, 120-A FETs, from Fairchild, part number FDP032N08 to see if they could be used for synchronous FETs QE and QF to hit our efficiency goals. After estimating the total FET losses and power budget it was determined that these FETs could be used in this design.

Equation 59.

Q E_{g} = 152 n C

Equation 60.

R_{d s (o n) Q E} = 3.2 m Ω

Calculate average FET C_OSS (C_{OSS_QE_AVG}) based on the data sheet parameters for C_OSS (C_{OSS_SPEC}), and drain to source voltage where C_{OSS_SPEC} was measured (V_{ds_spec}), and the maximum drain to source voltage in the design (V_dsQE) that will be applied to the FET in the application.

Voltage across FET QE and QF when they are off:

Equation 61.

V_{d s Q E} = \frac{{2 \times V}_{I N M A X}}{a 1} \approx 39 V

Voltage where FET C_OSS is specified and tested in the FET data sheet:

Equation 62.

V_{d s_s p e c} = 25 V

Specified output capacitance from FET data sheet:

Equation 63.

C_{O S S_S P E C} = 1810 p F

Average QE and QF C_OSS [2]:

Equation 64.

C_{O S S_Q E_A V G} = C_{O S S_S P E C} \sqrt{\frac{V_{d s Q E}}{V_{d s_s p e c}}} \approx 1.6 n F

QE and QF RMS current:

Equation 65.

I_{Q E_R M S} = I_{S R M S} = 36.0 A

To estimate FET switching loss the V_g vs. Q_g curve from the FET data sheet needs to be studied. First the gate charge at the beginning of the miller plateau needs to be determined (QE_{MILLER_MIN}) and the gate charge at the end of the miller plateau (QE_{MILLER_MAX}) for the given V_DS.

Figure 9-1 V_g vs. Q_g for QE and QF FETs

Maximum gate charge at the end of the miller plateau:

Equation 66.

Q E_{M I L L E R_M A X} \approx 100 n C

Minimum gate charge at the beginning of the miller plateau:

Equation 67.

Q E_{M I L L E R_M I N} \approx 52 n C

Note:

The FETs in this design were driven with UCC27324 setup to drive 4-A (I_P) of gate drive current.

Equation 68.

I_{P} \approx 4 A

Estimated FET V_ds rise and fall time:

Equation 69.

t_{r} \approx t_{f} = \frac{100 n C - 52 n C}{\frac{I_{P}}{2}} = \frac{48 n C}{\frac{4 A}{2}} \approx 24 n s

Estimate QE and QF FET Losses (P_QE):

Equation 70.

P_{Q E} = {I_{Q E_R M S}}^{2} \times R_{d s (o n) Q E} + \frac{P_{O U T}}{V_{O U T}} \times V_{d s Q E} (t_{r} + t_{f}) \frac{f_{s}}{2} + 2 \times C_{O S S_Q E_A V G} \times {V_{d s Q E}}^{2} \frac{f_{s}}{2} + 2 \times Q_{g Q E} \times V_{g Q E} \frac{f_{s}}{2}

Equation 71.

P_{Q E} \approx 9.3 W

Recalculate the power budget and check remaining power budget to hit efficency goal.

Equation 72.

P_{B U D G E T} = P_{B U D G E T} - 2 \times P_{Q E} \approx 6.5 W