SLUA560D June   2011  – March 2022 UCC28950 , UCC28950-Q1 , UCC28951 , UCC28951-Q1

 

  1.   Trademarks
  2. Design Specifications
  3. Functional Schematic
  4. Power Budget
  5. Transformer Calculations (T1)
  6. QA, QB, QC, QD FET Selection
  7. Selecting LS
  8. Output Inductor Selection (LOUT)
  9. Output Capacitance (COUT)
  10. Select FETs QE and QF
  11. 10Input Capacitance (CIN)
  12. 11Setting Up the Current Sense (CS) Network (CT, RS, RRE, DA)
  13. 12Voltage Loop and Slope Compensation
  14. 13Setting Turn-on Delays to Achieve Zero Voltage Switching (ZVS)
  15. 14Turning SR FETs-off Under Light Load Conditions
  16. 15600 W FSFB Detailed Schematic and Test Data
  17. 16References
  18. 17Revision History

Voltage Loop and Slope Compensation

The UCC28950/1 VREF output (Pin 1) needs a high frequency bypass capacitor to filter out high frequency noise. This pin needs at least 1 µF of high frequency bypass capacitance (CBP1). Please refer to figure 1 for proper placement.

Equation 96. CBP1=1 uF

The voltage amplifier reference voltage (Pin 2, EA +) can be set with a voltage divider (RA, RB), for this design example we are going to set the error amplifier reference voltage (V1) to 2.5 V. Select a standard resistor value for RB and then calculate resistor value RA.

UCC28950/1/1 reference voltage:

Equation 97. VREF=5 V

Set voltage amplifier reference voltage:

Equation 98. V1=2.5 V
Equation 99. RB=2.37 kΩ
Equation 100. RA=RB×VREF-V1V1=2.37 kΩ

Voltage divider formed by resistor RC and RI are chosen to set the DC output voltage (VOUT) at Pin 3 (EA-).

Select a standard resistor for RC:

Equation 101. RC=2.37 kΩ

Calculate RI:

Equation 102. RI=Rc×VOUT-V1V19 kΩ

Then choose a standard resistor for RI:

Equation 103. RI=9.09 kΩ

Compensating the feedback loop can be accomplished by properly selecting the feedback components (RF, CZ and CP). These components are placed as close to pin 3 and 4 as possible of the UCC28950/1.

Calculate load impedance at 10% load (RLOAD):

Equation 104. RLOAD=VOUT2POUT×0.1=2.4 Ω

Approximation of control to output transfer function (GCO(f)) as a function of frequency:

Equation 105. GCO(f)ΔVOUTΔVC=a1×a2×RLOADRS×1+2πj×f×ESRCOUT×COUT1+2πj×f×RLOAD×COUT×11+S(f)2π×fPP+S(f)2π×fPP2

Double pole frequency of GCO(f):

Equation 106. f P P f s 4 = 50   k H z

Angular velocity:

Equation 107. S ( f ) = 2 π × j × f

Compensate the voltage loop with type 2 feedback network. The following transfer function is the compensation gain as a function of frequency (GC(f)). Please refer to Figure 2-1 for component placement.

Equation 108. GC(f)=ΔVCΔVOUT=2πj×f×RF×CZ+12πj×f×CZ+CPRI2πj×f×CZ×CP×RFCZ+CP+1
Equation 109.

Calculate voltage loop feedback resistor (RF) based on crossing the voltage (fC) loop over at a 10th of the double pole frequency (fPP).

Equation 110. fC=fPP10=5 kHz
Equation 111. RF=RIGCOfPP1027.9 kΩ

Select a standard resistor for RF.

Equation 112. R F 27.4   k Ω

Calculate the feedback capacitor (CZ) to give added phase at crossover.

Equation 113. C Z = 1 2 × π × R F × f C 5 5.8 n F
Equation 114. CZ=5.6nF

Select a standard capacitance value for the design.

Put a pole at two times fC.

Equation 115. CP=12×π×RF×fC×2580pF

Select a standard capacitance value for the design.

Equation 116. CP=560pF

Loop gain as a function of frequency (TV(f)) in dB.

Equation 117. TVdB(f)=20logGC(f)×GCO(f)

Plot theoretical loop gain and phase to graphically check for loop stability (Figure 11-1). The theoretical loop gain crossed over at roughly 3.7 kHz with a phase margin of greater than 90 degrees.

Note:

It is wise to check your loop stability of your final design with transient testing and/or a network analyzer and adjust the compensation (GC(f)) feedback as necessary.

GUID-20211007-SS0I-Z1ZT-M4X2-VB41P23XT5TS-low.gif Figure 12-1 Loop Gain and Loop Phase

To limit over shoot during power up the UCC28950/1 has a soft-start function (SS, Pin 5) which in this application was set for a soft start time of 15 ms (tSS).

Equation 118. t s s = 15   m s
Equation 119. C s s = t s s × 25 u A V 1 + 0.55 123   n F

Select a standard capacitor for the design.

Equation 120. C s s = 150   n F

The UCC28950/1 also provides slope compensation for peak current mode control (Pin 12). This can be set by setting RSUM with the following equations. The following equations will calculate the required amount of slope compensation (VSLOPE) that is needed for loop stability.

Note:

The change in magnetizing current on the primary ΔILMAG contributes to slope compensation.

Equation 121. ILMAG=VIN1-DTYPLMAG×fs=234 mA

To help improve noise immunity VSLOPE is set to have a total slope that will equal 10% of the maximum current sense signal (0.2 V) over one inductor switching period.

Equation 122. V S L O P E 1 = 0.2 V × f s × 0.04 V u s
Equation 123. VSLOPE2=0.2V×fs-ILOUTa1×2-ILMAG×RS1-DTYP×fSa2=0.04Vus

If VSLOPE2 < VSLOPE1 set VSLOPE = VSLOPE1

If VSLOPE2 ≥ VSLOPE1 set VSLOPE = VSLOPE2

Equation 124. R S U M = 2.5 V × 1 0 3 Ω V S L O P E × 0.5 u s 125.4   k Ω

Select a standard resistor for RSUM.

Equation 125. R S U M = 127   k Ω