SLUAAC5 August   2021 UCC28700 , UCC28701 , UCC28702 , UCC28703 , UCC28704 , UCC28710 , UCC28711 , UCC28712 , UCC28713 , UCC28720 , UCC28722 , UCC28730 , UCC28740 , UCC28742 , UCC28910 , UCC28911

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Brief Review of DCM FM, AM, FM Flyback Control Law
  4. 3 Input (VIN) and Output (VOUT) Voltage Sensing for UVLO and OVP Fault Protection
  5. 4 Input Under Voltage Lockout (UVLO) Protection
  6. 5 Output Overvoltage (OVP) Protection
  7. 6 Not Recognizing a UVLO or OVP Fault
  8. 7 Separate Bias Supply Startup Issue and Resolution
  9. 8 Not Having a Clean Aux Winding Signal
  10. 9 Removing Aux Winding Ringing to Resolve False Triggering of OVP and UVLO Faults
  11. 10Noise on CS Pin Tripping Over Current Protection (OCP)
  12. 11Summary
  13. 12References

7 Separate Bias Supply Startup Issue and Resolution

When starting up a prototype flyback converter some engineers use a separate bias supply for powering VDD of the flyback controller. Some of these designers have mentioned that there are no gate driver pulses observed and the flyback controller appears to be not functioning. Most of the time the issue is when power was applied to VDD there was no input voltage applied to the flyback converter. The flyback converter had already sampled the input voltage and because there was none present the controller entered input UVLO fault protection. The gate driver stopped switching and the external bias supply is prevents cycling of the VDD pin between VVDD(off), VVDD(on) and VVDD(off) to reset the fault.

To resolve this issue apply the input voltage to VIN that is greater than the UVLO trip point. Then bring the bias voltage to VDD above VVDD(on). The other option is adjust the bias voltage at VDD below VVDD(off) and then above VVDD(on) to reset and clear the UVLO fault.