SLUS720F February   2007  – June 2019 TPS40195

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Dissipation Ratings
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable Functionality
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Oscillator and Synchronization
      4. 8.3.4  Undervoltage Lockout (UVLO)
      5. 8.3.5  Soft Start
      6. 8.3.6  Selecting the Short Circuit Threshold
      7. 8.3.7  5-V Regulator
      8. 8.3.8  Prebias Start-up
      9. 8.3.9  Drivers
      10. 8.3.10 Power Good
      11. 8.3.11 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application 1
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Output Inductor, LOUT
          2. 9.2.1.2.2 Output Capacitor, COUT
          3. 9.2.1.2.3 Input Capacitor, CIN
          4. 9.2.1.2.4 Switching MOSFET, QSW
          5. 9.2.1.2.5 Rectifier MOSFET, QSR
          6. 9.2.1.2.6 Component Selection for the TPS40195
            1. 9.2.1.2.6.1 Timing Resistor, RT
            2. 9.2.1.2.6.2 Setting UVLO
            3. 9.2.1.2.6.3 Setting the Soft-Start Time
            4. 9.2.1.2.6.4 Short-Circuit Protection, RILIM
            5. 9.2.1.2.6.5 Voltage Decoupling Capacitors, CBP, and CVDD
            6. 9.2.1.2.6.6 Boost Voltage, CBOOST and DBOOST (optional)
            7. 9.2.1.2.6.7 Closing the Feedback Loop RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2 AND CPZ1
          7. 9.2.1.2.7 Application Curve
      2. 9.2.2 Typical Application 2
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Typical Application 3
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Related Parts
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.4 Electrical Characteristics

TJ = –40°C to 85°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE
VFB Feedback voltage range 0°C ≤ TJ ≤ 85°C 588 591 594 mV
-40°C ≤ TJ ≤ 85°C 585 591 594
INPUT SUPPLY
VVDD Input voltage range 4.5 20 V
IVDD Operating current VEN = 3 V 4 mA
VEN < 0.6 V, VVDD = 12 V 165 250 μA
VEN < 0.6 V, VVDD = 20 V 230 330
ON BOARD REGULATOR
VBP Output voltage VVDD > 6 V, IBP ≤ 10 mA 5.1 5.3 5.5 V
VDO Regulator dropout voltage, VVDD - VBP VVDD = 5 V, IBP ≤ 25 mA 350 550 mV
ISC Regulator current limit threshold 75 mA
IBP Average current 75
OSCILLATOR
fSW Switching frequency VRT = VBP 400 500 580 kHz
VRT = 0 V 200 250 290
RRT = 100 kΩ 250
VRMP Ramp amplitude(1) 1 V
SYNCHRONIZATION
VINH High-level input voltage 2.5 V
VINL Low-level input voltage 0.5
TF(max) Maximum input fall time(1) 100 ns
VOH High-level output voltage ISYNC = 100 μA, sourcing 3.5 V
VOL Low-level output voltage ISYNC = 100 μA, sinking 0.3
TF Output fall time(1) CSYNC =25 pF 10 25 ns
TR Output rise time(1) 100 300
PWM
DMAX Maximum duty cycle(1) 85%
tON(min) Minimum controlled pulse(1) 130 ns
tDEAD Output driver dead time HDRV off to LDRV on 50
LDRV off to HDRV on 25
SOFT START
tSS Soft-start time VSS_SEL = 0 V, fSW = 250 kHz 4.8 ms
VSS_SEL = 0 V, fSW = 500 kHz 2.4
VSS_SEL = Floating, fSW = 250 kHz 2.4
VSS_SEL = Floating, fSW = 500 kHz 1.2
VSS_SEL = VBP, fSW = 250 kHz 1.2
VSS_SEL = VBP, fSW = 500 kHz 0.6
ERROR AMPLIFIER
GBWP Gain bandwidth product(1) 7 10 MHz
AOL DC gain(1) 60 dB
IFB Input bias current (current out of FB pin) 100 nA
IEAOP Output source current VFB = 0 V 1 mA
IEAOM Output sink current VFB = 2 V 1
SHORT-CIRCUIT PROTECTION
tPSS(min) Minimum pulse during short circuit(1) 250 ns
tBLNK Blanking time(1) 60 90 120
tOFF Off-time between restart attempts 40 ms
IILIM ILIM pin bias current TJ = 25°C 7 9 11 μA
VILIMOFST Low side comparator offset voltage -20 0 20 mV
VILIMH Short circuit threshold voltage on high-side MOSFET TJ = 25°C 400 550 650 mV
OUTPUT DRIVERS
RHDHI High-side driver pull-up resistance VBOOT - VSW = 4.5 V, IHDRV = -100 mA 3 6 Ω
RHDLO High-side driver pull-down resistance VBOOT - VSW = 4.5 V, IHDRV = 100 mA 1.5 3.0
RLDHI Low-side driver pull-up resistance ILDRV = -100 mA 2.5 5.0
RLDLO Low-side driver pull-down resistance ILDRV = 100 mA 0.8 1.5
tHRISE High-side driver rise time(1) CLOAD = 1 nF 15 35 ns
tHFALL High-side driver fall time(1) 10 25
tLRISE Low-side driver rise time(1) 15 35
tLFALL Low-side driver fall time(1) 10 25
UVLO
VUVLOBP BP5 UVLO threshold voltage 3.9 4.1 4.3 V
VUVLOBPH BP5 UVLO hysteresis voltage 800 mV
VUVLO Turn-on voltage 1.125 1.26 1.375 V
IUVLO UVLO pin hysteresis current VUVLO = 1.375 V 5.2 μA
SHUTDOWN
VIH High-level input voltage, EN 1.9 3 V
VIL Low-level input voltage, EN 0.6
POWER GOOD
VOV Feedback voltage limit for power good 650 mV
VUV Feedback voltage limit for power good 530
VPG_HYST Powergood hysteresis voltage at FB pin 30
RPGD Pulldown resistance of PGD pin VFB < 530 mV or VFB > 650 mV 7 20 Ω
IPDGLK Leakage current 530 mV ≤ VFB ≤ 650 mV VPGOOD = 5V 7 12 μA
BOOT DIODE
VDFWD Bootstrap diode forward voltage IBOOT = 5 mA 0.5 0.8 1.2 V
THERMAL SHUTDOWN
TJSD Junction shutdown temperature(1) 150 °C
TJSDH Hysteresis(1) 20
(1) Specified by design. Not production tested.