SLUSDO8A March   2020  – January 2025 BQ24800

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Power Up
        1. 6.3.1.1 Battery Only
        2. 6.3.1.2 Adapter Detect and ACOK Output
          1. 6.3.1.2.1 Adapter Overvoltage (ACOV)
        3. 6.3.1.3 REGN LDO
      2. 6.3.2 System Power Selection
      3. 6.3.3 Current and Power Monitor
        1. 6.3.3.1 High Accuracy Current Sense Amplifier (IADP and IDCHG)
        2. 6.3.3.2 High Accuracy Power Sense Amplifier (PMON)
      4. 6.3.4 Processor Hot Indication for CPU Throttling
      5. 6.3.5 Input Current Dynamic Power Management
        1. 6.3.5.1 Setting Input Current Limit
      6. 6.3.6 Two-Level Adapter Current Limit (Peak Power Mode)
      7. 6.3.7 EMI Switching Frequency Adjust
      8. 6.3.8 Device Protections Features
        1. 6.3.8.1 Charger Timeout
        2. 6.3.8.2 Input Overcurrent Protection (ACOC)
        3. 6.3.8.3 Charge Overcurrent Protection (CHG_OCP)
        4. 6.3.8.4 Battery Overvoltage Protection (BATOVP)
        5. 6.3.8.5 Battery Short
        6. 6.3.8.6 Thermal Shutdown Protection (TSHUT)
        7. 6.3.8.7 Inductor Short, MOSFET Short Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Battery Charging in Buck Mode
        1. 6.4.1.1 Setting the Charge Current
        2. 6.4.1.2 Setting the Charge Voltage
        3. 6.4.1.3 Automatic Internal Soft-Start Charger Current
      2. 6.4.2 Hybrid Power Boost Mode
      3. 6.4.3 Battery Only Boost Mode
        1. 6.4.3.1 Setting Minimum System Voltage in Battery Only Boost Mode
      4. 6.4.4 Battery Discharge Current Regulation in Hybrid Boost Mode and Battery Only Boost Mode
      5. 6.4.5 Battery LEARN Cycle
      6. 6.4.6 Converter Operational Modes
        1. 6.4.6.1 Continuous Conduction Mode (CCM)
        2. 6.4.6.2 Discontinuous Conduction Mode (DCM)
        3. 6.4.6.3 Non-Sync Mode and Light Load Comparator
    5. 6.5 Programming
      1. 6.5.1 SMBus Interface
        1. 6.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 6.5.1.2 Timing Diagrams
    6. 6.6 Register Maps
      1. 6.6.1  Battery-Charger Commands
      2. 6.6.2  Setting Charger Options
        1. 6.6.2.1 ChargeOption0 Register
      3. 6.6.3  ChargeOption1 Register
      4. 6.6.4  ChargeOption2 Register
      5. 6.6.5  ChargeOption3 Register
      6. 6.6.6  ProchotOption0 Register
      7. 6.6.7  ProchotOption1 Register
      8. 6.6.8  ProchotStatus Register
      9. 6.6.9  Charge Current Register
      10. 6.6.10 Charge Voltage Register
      11. 6.6.11 Discharge Current Register
      12. 6.6.12 Minimum System Voltage Register
      13. 6.6.13 Input Current Register
      14. 6.6.14 Register Exceptions
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical System Schematic
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Adapter Current Sense Filter
          2. 7.2.1.2.2  Negative Output Voltage Protection
          3. 7.2.1.2.3  Reverse Input Voltage Protection
          4. 7.2.1.2.4  Reduce Battery Quiescent Current
          5. 7.2.1.2.5  CIN Capacitance
          6. 7.2.1.2.6  L1 Inductor Selection
          7. 7.2.1.2.7  CBATT Capacitance
          8. 7.2.1.2.8  Buck Charging Internal Compensation
          9. 7.2.1.2.9  CSYS Capacitance
          10. 7.2.1.2.10 Battery Only Boost Internal Compensation
          11. 7.2.1.2.11 Power MOSFETs Selection
          12. 7.2.1.2.12 Input Filter Design
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Migration from Previous Devices (Does not Support Battery Only Boost)
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 CSYS Capacitance
        3. 7.2.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Examples
      1. 9.2.1 Layout Consideration of Current Path
      2. 9.2.2 Layout Consideration of Short Circuit Protection
      3. 9.2.3 Layout Consideration for Short Circuit Protection
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.6.6 ProchotOption0 Register

Figure 6-10 ProchotOption0 Register (0x3C)
15141312111098
ReservedILIM2_VTH[3:0]ICRIT_DEGReserved
RR/WR/WR
76543210
VBATT_VTH[1:0]EN_PROCHOT_EXTPROCHOT_WIDTH[1:0]PROCHOT_CLEARINOM_DEGINOM_VTH
R/WR/WR/WR/WR/WR/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-10 ProchotOption0 Register (0x3C)
BITBIT NAMEDESCRIPTION
[15]Reserved 0 - Reserved
[14:11]Peak Adapter Current Limit
(ILIM2_VTH)		ILIM2 threshold as percentage of DPM in REG0x3F(). At 250% setting, when IDPM is over 3.648A, clamp ILIM2 to 230% of IDPM.
The current is measured on the RAC between ACP and ACN. ICRIT is set as 110% of ILIM2.
0001 - 1001: 110% - 150%, step 5%
1001: 150%, 1010: 160%, 1011: 170%, 1100: 180%, 1101: 200%, 1110: 220%; 1111: 250%
Default 150% (1001)
[10:9]ICRIT Deglitch Time
(ICRIT_DEG)		Typical ICRIT deglitch time.
00: 10 µs
01: 100 µs (default at POR)
10: 400 µs
11: 800 µs
[8]Reserved0 - Reserved
[7:6]Battery Voltage Threshold
(VBATT_VTH)		Battery voltage threshold to trigger PROCHOT.
Measure on SRN with fixed 20-µs deglitch time. Trigger when SRN voltage is below the threshold.
If REG0x15() is programmed below VBATT threshold, it is recommended to not enable VBATT in PROCHOT profile.
00: 5.75 V
01: 6.00 V (default at POR)
10: 6.25 V
11: 6.50 V
[5]PROCHOT Pulse Extension Enable
(EN_PROCHOT_EXT)		When pulse extension is enabled, keep PROCHOT pin voltage low until host write 0x3C[2] = 0.
0: Disable pulse extension (default at POR)
1: Enable pulse extension
[4:3]PROCHOT Pulse Width
(PROCHOT_WIDTH[1:0])		Minimum PROCHOT pulse width when REG0x3C[5]=0
00: 100 µs
01: 1 ms
10: 10 ms (default at POR)
11: 5 ms
[2]PROCHOT Pulse Clear
(PROCHOT_CLEAR)		Clear PROCHOT pulse when (0x3C[5] = 1).
0: Clear PROCHOT pulse and drive PROCHOT pin HIGH
1: Idle (default at POR)
[1]INOM Deglitch Time
(INOM_DEG)		Maximum INOM deglitch time. INOM threshold is 110% of DPM in REG0x3F(). Measure current between ACP and ACN. Trigger when the current is above this threshold.
0: 1 ms (max) (default at POR)
1: 15 ms (max)
[0]INOM Threshold
(INOM_VTH)		INOM current threshold as percentage of DPM in REG0x3F().
0: 110% (default at POR)
1: 106%