SLUSDO8A March   2020  – January 2025 BQ24800

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Power Up
        1. 6.3.1.1 Battery Only
        2. 6.3.1.2 Adapter Detect and ACOK Output
          1. 6.3.1.2.1 Adapter Overvoltage (ACOV)
        3. 6.3.1.3 REGN LDO
      2. 6.3.2 System Power Selection
      3. 6.3.3 Current and Power Monitor
        1. 6.3.3.1 High Accuracy Current Sense Amplifier (IADP and IDCHG)
        2. 6.3.3.2 High Accuracy Power Sense Amplifier (PMON)
      4. 6.3.4 Processor Hot Indication for CPU Throttling
      5. 6.3.5 Input Current Dynamic Power Management
        1. 6.3.5.1 Setting Input Current Limit
      6. 6.3.6 Two-Level Adapter Current Limit (Peak Power Mode)
      7. 6.3.7 EMI Switching Frequency Adjust
      8. 6.3.8 Device Protections Features
        1. 6.3.8.1 Charger Timeout
        2. 6.3.8.2 Input Overcurrent Protection (ACOC)
        3. 6.3.8.3 Charge Overcurrent Protection (CHG_OCP)
        4. 6.3.8.4 Battery Overvoltage Protection (BATOVP)
        5. 6.3.8.5 Battery Short
        6. 6.3.8.6 Thermal Shutdown Protection (TSHUT)
        7. 6.3.8.7 Inductor Short, MOSFET Short Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Battery Charging in Buck Mode
        1. 6.4.1.1 Setting the Charge Current
        2. 6.4.1.2 Setting the Charge Voltage
        3. 6.4.1.3 Automatic Internal Soft-Start Charger Current
      2. 6.4.2 Hybrid Power Boost Mode
      3. 6.4.3 Battery Only Boost Mode
        1. 6.4.3.1 Setting Minimum System Voltage in Battery Only Boost Mode
      4. 6.4.4 Battery Discharge Current Regulation in Hybrid Boost Mode and Battery Only Boost Mode
      5. 6.4.5 Battery LEARN Cycle
      6. 6.4.6 Converter Operational Modes
        1. 6.4.6.1 Continuous Conduction Mode (CCM)
        2. 6.4.6.2 Discontinuous Conduction Mode (DCM)
        3. 6.4.6.3 Non-Sync Mode and Light Load Comparator
    5. 6.5 Programming
      1. 6.5.1 SMBus Interface
        1. 6.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 6.5.1.2 Timing Diagrams
    6. 6.6 Register Maps
      1. 6.6.1  Battery-Charger Commands
      2. 6.6.2  Setting Charger Options
        1. 6.6.2.1 ChargeOption0 Register
      3. 6.6.3  ChargeOption1 Register
      4. 6.6.4  ChargeOption2 Register
      5. 6.6.5  ChargeOption3 Register
      6. 6.6.6  ProchotOption0 Register
      7. 6.6.7  ProchotOption1 Register
      8. 6.6.8  ProchotStatus Register
      9. 6.6.9  Charge Current Register
      10. 6.6.10 Charge Voltage Register
      11. 6.6.11 Discharge Current Register
      12. 6.6.12 Minimum System Voltage Register
      13. 6.6.13 Input Current Register
      14. 6.6.14 Register Exceptions
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical System Schematic
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Adapter Current Sense Filter
          2. 7.2.1.2.2  Negative Output Voltage Protection
          3. 7.2.1.2.3  Reverse Input Voltage Protection
          4. 7.2.1.2.4  Reduce Battery Quiescent Current
          5. 7.2.1.2.5  CIN Capacitance
          6. 7.2.1.2.6  L1 Inductor Selection
          7. 7.2.1.2.7  CBATT Capacitance
          8. 7.2.1.2.8  Buck Charging Internal Compensation
          9. 7.2.1.2.9  CSYS Capacitance
          10. 7.2.1.2.10 Battery Only Boost Internal Compensation
          11. 7.2.1.2.11 Power MOSFETs Selection
          12. 7.2.1.2.12 Input Filter Design
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Migration from Previous Devices (Does not Support Battery Only Boost)
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 CSYS Capacitance
        3. 7.2.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Examples
      1. 9.2.1 Layout Consideration of Current Path
      2. 9.2.2 Layout Consideration of Short Circuit Protection
      3. 9.2.3 Layout Consideration for Short Circuit Protection
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.6.3 ChargeOption1 Register

Figure 6-7 ChargeOption1 Register (0x3B)
15141312111098
BAT_DEPL_VTHRSNS_RATIOEN_IDCHGEN_PMONPMON_RATIOReserved
R/WR/WR/WR/WR/WR
76543210
CMP_REFCMP_POLCMP_DEGEN_FET_LATCHOFFReservedEN_SHIP_DCHGReserved
R/WR/WR/WR/WRR/WR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-7 ChargeOption1 Register (0x3B)
BITBIT NAMEDESCRIPTION
[15:14]Battery Depletion Threshold (BAT_DEPL_VTH)Battery over-discharge threshold. During LEARN cycle, when battery voltage is below the depletion threshold, the IC exits LEARN mode. During boost mode, when battery voltage is below the depletion threshold, the IC exits boost mode.
00: Falling threshold = 60% of ChargeVoltage() register setting
01: Falling threshold = 64% of ChargeVoltage() register setting
10: Falling threshold = 68% of ChargeVoltage() register setting
11: Falling threshold = 72% of ChargeVoltage() register setting (default at POR)
[13:12]RAC and RSR Ratio
(RSNS_RATIO)		Adjust the PMON calculation for different input sense resistor RAC and charge sense resistor RSR ratio. Reference Table 6-1 for further detail..
00: RAC and RSR 1:1 (default at POR)
01: RAC and RSR 2:1
10: RAC and RSR 1:2
11: Reserved
[11]IDCHG Buffer Enable
(EN_IDCHG)		IDCHG pin output enable.
0: Disable IDCHG output to minimize Iq (default at POR)
1: Enable IDCHG output
[10]PMON Buffer Enable
(EN_PMON)		PMON pin output enable.
0: Disable PMON output to minimize Iq (default at POR)
1: Enable PMON output
[9]PMON Gain
(PMON_RATIO)		Ratio of PMON output current vs total input and battery power. Reference Table 6-1 for further detail.
0: 0.25 µA/W for 10 mΩ sense resistors
1: 1 µA/W for 10 mΩ sense resistors (default at POR)
[8]Reserved0 - Reserved
[7]Independent Comparator Reference (CMP_REF)Independent comparator internal reference.
0: 2.3 V (default at POR)
1: 1.2 V
[6]Independent Comparator Polarity (CMP_POL)Independent comparator output polarity.

With comparator polarity bit set as 1, the hysteresis is set by placing a resistor from CMPIN to CMPOUT. With comparator polarity bit set as 0, the hysteresis is internally set as 100mV.


0: When CMPIN is above internal threshold, CMPOUT is LOW (default at POR)
1: When CMPIN is above internal threshold, CMPOUT is HIGH
[5:4]Independent Comparator Deglitch Time (CMP_DEG)Independent comparator deglitch time, applied on the edge where CMPOUT goes LOW. No deglitch time is applied on the rising edge of CMPOUT. If the value in REG0x3B[7:3] is changed by host, deglitch time will get reset.
00: Independent comparator is disabled
01: Independent comparator is enabled with output deglitch time 1 µs
Note: 1 µs deglitch should not be used when low-power mode bit is enabled.
10: Independent comparator is enabled with output deglitch time 2 ms  (default at POR)
11: Independent comparator is enabled with output deglitch time 5 sec
[3]Power Path Latch-off Enable (EN_FET_LATCHOFF )When independent comparator is triggered, both ACFET/RBFET turn off. The latch off is cleared by either POR or write this bit to zero. This function is available with CMP_DEG setting of 2 ms (10) or 5 sec (11).
0: When independent comparator is triggered, no power path latch off (default at POR)
1: When independent comparator is triggered, power path latches off.
[2]Reserved0 - Reserved
[1]Discharge SRN for Shipping Mode (EN_SHIP_DCHG)Discharge SRN pin for 140 ms with minimum 5-mA current.
0: Disable discharge mode (default at POR)
1: Enable discharge mode
[0]Reserved0 - Reserved