SLUSF69A May   2024  – January 2025 BQ25186

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Battery Charging Process
        1. 6.1.1.1 Trickle Charge
        2. 6.1.1.2 Pre-Charge
        3. 6.1.1.3 Fast Charge
        4. 6.1.1.4 Termination
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Voltage Based Dynamic Power Management (VINDPM)
      2. 6.3.2  Dynamic Power Path Management Mode (DPPM)
      3. 6.3.3  Battery Supplement Mode
      4. 6.3.4  Sleep Mode
      5. 6.3.5  SYS Power Control (SYS_MODE bit control)
        1. 6.3.5.1 SYS Pulldown Control
      6. 6.3.6  SYS Regulation
      7. 6.3.7  ILIM Control
      8. 6.3.8  Protection Mechanisms
        1. 6.3.8.1 Input Overvoltage Protection
        2. 6.3.8.2 Battery Undervoltage Lockout
        3. 6.3.8.3 Battery Overcurrent Protection
        4. 6.3.8.4 System Overvoltage Protection
        5. 6.3.8.5 System Short Protection
        6. 6.3.8.6 Thermal Protection and Thermal Regulation
        7. 6.3.8.7 Safety Timer and Watchdog Timer
      9. 6.3.9  Pushbutton Wake and Reset Input
        1. 6.3.9.1 Pushbutton Wake or Short Button Press Functions
        2. 6.3.9.2 Pushbutton Reset or Long Button Press Functions
      10. 6.3.10 15-Second Timeout for HW Reset
      11. 6.3.11 Hardware Reset
      12. 6.3.12 Software Reset
      13. 6.3.13 Interrupt Indicator (/INT) Pin
      14. 6.3.14 Power Good (PG) / General Purpose Output Pin
      15. 6.3.15 External NTC Monitoring (TS)
        1. 6.3.15.1 TS Biasing and Function
      16. 6.3.16 I2C Interface
        1. 6.3.16.1 F/S Mode Protocol
    4. 6.4 Device Functional Modes
    5. 6.5 Register Maps
      1. 6.5.1 I2C Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

BQ25186 DLH Package 10 Pin (Top View)Figure 4-1 DLH Package 10 Pin (Top View)
Table 4-1 Pin Functions
PINI/O(1)DESCRIPTION
NAMENO.
IN10PDC Input Power Supply. IN is connected to the external DC supply. Bypass IN to GND with at least 1 μF of capacitance using a ceramic capacitor. Due to DC Bias derating, higher input voltages require larger capacitors to ensure at least 1 μF of effective capacitance.
SYS1PRegulated System Output. Connect at least 10-μF ceramic capacitor (at least 1 μF of ceramic capacitance with DC bias de-rating) from SYS to GND as close to the SYS and GND pins as possible.
BAT2PBattery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with at least 1 μF of ceramic capacitance.
GND5-Ground connection. Connect to the ground plane of the circuit.
SCL8I/OI2C Interface Clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA7I/OI2C Interface Data. Connect SDA to the logic rail through a 10-kΩ resistor.
/INT9OINT is an open-drain output that signals fault interrupts. When a fault occurs, a 128-μs active low pulse is sent out as an interrupt for the host. INT is enabled/disabled using the MASK_INT bit in the control register. Can be pulled up to a 1- to 20-kΩ resistor. Typical pull-up voltage = 1.8 V, max pull-up voltage = 5 V.
TS/MR6I/OManual Reset Input/ NTC thermistor pin. TSMR is a general purpose input that must be held low for greater than tLPRESS to go into Shipmode or perform a hardware reset. It can also be used to detect shorter button press durations such as twake1 and twake2 TSMR may be driven by a momentary push-button or a MOS switch. The TSMR pin will also have an NTC thermistor connected on to it.
/CE4ICharge Enable Pin. Drive /CE low or leave disconnected to enable charging when VIN VIN is valid. Drive /CE high to disable charge. Has an internal pulldown resistor of around 5 MΩ. This pin has no effect when VIN is not present
/PG/GPO3OOpen-drain power good (PG) indicator output. Connect /PG/GPO to the logic rail through a 1-kΩ to 100-kΩ resistor, or use an LED for visual indication. can also be configured via I2C as a general-purpose output (GPO) to sink current.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.