SLUSG02 May   2025 TPS6286A06D

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. 6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Save Mode (PFM)
      2. 7.3.2 Forced PWM Mode
      3. 7.3.3 Low Dropout Operation (100% Duty Cycle)
      4. 7.3.4 Soft Start
      5. 7.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 Thermal Warning and Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable and Disable (EN)
      2. 7.4.2 Output Discharge
      3. 7.4.3 Power Good (PG)
      4. 7.4.4 Voltage Setting and Mode Selection (VSET/MODE)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting the Output Voltage
        3. 8.2.2.3 Output Filter Design
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

TJ = –40°C to 125°C, and VIN = 2.4V to 5.5V. Typical values are at TJ = 25°C and VIN = 5V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ_VIN Quiescent current EN = High, no load, device not switching, TJ = 25℃  5.1 9 µA
IQ_OUT Operating quiescent current into OUT pin EN = High, no load, device not switching, VOUT = 1.8V, TJ = 25℃  18 µA
ISD Shutdown current EN = Low, TJ = 25℃, EN has not been triggered once
 		 0.24 0.75 µA
ISD Shutdown current VIN=5V, TJ = 25℃, EN = Low, after EN has been triggered once 6.5 µA
VUVLO Undervoltage lock out threshold VIN rising 2.2 2.3 2.4 V
VIN falling 2.1 2.2 2.3 V
TJSD Thermal shutdown threshold TJ rising 150 °C
Thermal shutdown hysteresis TJ falling 20 °C
LOGIC INTERFACE
VIH High-level input threshold voltage at EN and VSET/MODE 0.9 V
VIL Low-level input threshold voltage at EN and VSET/MODE 0.4 V
RPull_down_VSET_MODE Pull-down resistor on VSET/MODE pin TJ=25 ℃ , VIN= 5V, VVSET/MODE= 5V, After R2D read is completed. 3.3 MΩ
IEN,LKG Input leakage current into EN pin TJ = 25℃, VIN= 5.0V, VEN= 0.4V 0.01 0.1 µA
RPull_down_EN Pull-down resistor on EN pin TJ=25 ℃ , VIN= 5V, VEN= 5V 2.25  MΩ
STARTUP, POWER GOOD
tDelay Enable delay time Time from EN high to device starts switching
249kΩ resistor connected between VSET/MODE and GND		 420 840 1200 µs
tRamp Output voltage ramp time Time from device starts switching to power good (no external capacitor connected) 1 1.5 1.85 ms
RPull_up_PG PG INTERNAL Pull Up Resistor to VIN TJ=25 ℃  500 kΩ
VPG Power-good lower threshold VOUT referenced to VOUT nominal  85 91 96 %
Power-good upper threshold VOUT referenced to VOUT nominal  103 111 120 %
VPG,OL Low-level output voltage Isink = 1mA 0.36  V
Iss SS pin source current 20 µA
tPG,DLY Power-good deglitch delay Rising and falling edges 34 µs
OUTPUT
VOUT Output voltage accuracy Fixed voltage operation, FPWM, no load, TJ = 25°C –0.7 0.7 %
VOUT Output voltage accuracy Fixed voltage operation, FPWM, no load –1 1 %
VFB Feedback voltage Adjustable voltage operation 594 600 606 mV
IFB,LKG Input leakage into FB pin Adjustable voltage operation, VFB = 0.6V, TJ = 25℃ 0.01 0.1  µA
RDIS Output discharge resistor at OUT pin 4.3 Ω
Load regulation VOUT = 0.9V, FPWM  0.04 %/A
POWER SWITCH
RDS(on) High-side FET on-resistance 8 mΩ
Low-side FET on-resistance 8 mΩ
ILIM High-side FET forward current limit 7.3 8 9 A
ILIM Low-side FET forward current limit 6.5 A
ILIM Low-side FET negative current limit –3 A
fSW PWM switching frequency IOUT = 1A, VOUT = 0.9V 1.2 MHz