SLUSG05 March   2025 UC2843L-Q1 , UC2844L-Q1 , UC2845L-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pulse-by-Pulse Current Limiting
      2. 7.3.2 Current Sense Circuit
      3. 7.3.3 Error Amplifier Configuration
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Oscillator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Undervoltage Lockout (UVLO) Start-Up
      3. 7.4.3 UVLO Turnoff Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 UC2842A (UC284xL-Q1) Design Procedure
      3. 8.2.3 Application Curves
      4. 8.2.4 Power Supply Recommendations
      5. 8.2.5 Layout
        1. 8.2.5.1 Layout Guidelines
        2. 8.2.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

UC2843L-Q1 UC2844L-Q1 UC2845L-Q1 D Package, 8-Pin SOIC (Top View) Figure 5-1 D Package, 8-Pin SOIC (Top View)
Table 5-1 Pin Functions
PINI/ODESCRIPTION
NAMENO.
COMP1OOutputs the low impedance 1MHz internal error amplifier that is also the input to the peak current limit or PWM comparator, with an open-loop gain (AVOL) of 80dB. This pin is capable of sinking a maximum of 6mA and is not internally current limited.
FB2IInput to the error amplifier that can be used to control the power converter voltage-feedback loop for stability.
GND5—This is the controller signal ground.
ISENSE3IInput to the peak current limit, PWM comparator of the UC284xL-Q1 controller. When used in conjunction with a current sense resistor, the error amplifier output voltage controls the power systems cycle-by-cycle peak current limit. The maximum peak current sense signal is internally clamped to 1V. See Section 7.2.
OUTPUT6OOutput of 1A totem pole gate driver. This pin can sink and source up to 1A of gate driver current. A gate driver resistor must be used to limit the gate driver current.
RT/CT4IInput to the internal oscillator that is programmed with an external timing resistor (RT) and timing capacitor (CT). See Section 7.3.5 for information on properly selecting these timing components. TI recommends using capacitance values from 470pF to 4.7nF. TI also recommends that the timing resistor values chosen be from 5kΩ to 100kΩ.
VCC7IBias input to the gate driver. This pin must have a biasing capacitor that is at least 10 times greater than the gate capacitance of the main switching FET used in the design.
VREF8OReference voltage output of the PWM controller. This pin must supply no more than 10mA under normal operation. This output is short-circuit protected at roughly 100mA. This reference is also used for internal comparators and needs a high frequency bypass capacitor of 1µF. The VCC capacitor also must be at least 10 times greater than the capacitor on the VREF pin.