This application design procedure shows how to setup and use the UC2842A peak current mode controller in an offline flyback converter, with universal input to a 12-V, 48-W regulated output. The same process can be applied to UC284xL-Q1 family.

Setting up and designing with the UC2842A peak current mode controller in a continuous mode flyback application requires knowing some things about the power stage. First, calculate the required input bulk capacitance (C_IN) based on output power level (P_OUT), efficiency (ƞ), minimum input voltage (V_IN(min)), line frequency (f_LINE) and minimum bulk voltage. For this design example let V_BULK(min) = 95V.

Equation 2.

Equation 3.

The output capacitor (C_OUT) is sized so the output voltage does not droop more than 10% during a large-signal transient response. The voltage-loop crossover frequency (f_C) is estimated to be 2.5kHz at this point in the design.

Equation 4.

The C_OUT selected for the design is a 2200-µF capacitor, with an equivalent series resistance (ESR) of 45mΩ.

Next calculate the maximum primary to secondary turns ratio (N_PS) of the transformer, based on the minimum input voltage and output voltage.

Equation 5.

Next calculate the auxiliary to secondary turns ratio (N_AS) of the transformer, based on the output voltage and the bias voltage of the UC2842A.

Equation 6.

Once the transformer turns ratios have been determined, the minimum primary magnetizing inductance (L_PM) of the transformer can be calculated based on minimum bulk voltage, Duty Cycle (D), reflected output current and efficiency. The transformer used in this design has an L_PM of 1.7mH, N_PS = 10, and a N_AS = 1, f_sw = 100kHz

Equation 7.

Equation 8.

After the transformer has been selected, the primary peak current (I_LpPK) of the transformer can be calculated based on the primary magnetizing inductance ripple (I_LPM) and the reflected output current across the transformer.

Equation 9.

Equation 10.

Once the primary peak current has been calculated the current sense resistor (R_CS) can be selected.

Equation 11.

Resistors R_S1 and R_S2 are used to set the slope compensation of the design. Capacitor C_S1 is a DC blocking capacitor, and pull-up resistor R_P is used to provide some offset to the current sense signal for noise immunity. R_P and R_S2 were preselected to add a DC offset of 50mV to the current sense signal.

R_S1 is selected to set the slope compensation to one-half of the ripple current down slope of the flyback inductor. This can be accomplished by calculating the secondary magnetizing inductance (L_SM) and using the following calculation for R_S1. The 1.7V in the R_S1 equation is the peak-to-peak ripple voltage amplitude of the oscillator.

Equation 12.

where

Resistors R_I and R_K are selected to the output reference and can be calculated by preselecting a value for R_K and knowing the TL431 reference voltage (V_TL431REF). After choosing 2.49 kΩ for R_K, R_I is calculated and a standard resistor value of 9.53kΩ is chosen for this resistor.

Equation 13.

This design using the UC3842A controller has an interesting control loop with many components. G_OPTO(f) is the approximate transfer function across the opto isolator in the design. The pole frequency of the opto isolator is represented by f_P. The opto isolator used in this design has a current transfer ratio of 1 and pole frequency of roughly 5kHz. See Figure 8-1 for component placement and node voltages. The voltage loop (f_C) must cross-over less than the opto isolator pole for simplified compensation.

Equation 14.

Equation 15.

Equation 16.

G_BC(f) is an estimate of the transfer function from the output of the opto isolator to the PWM’s control voltage .

Equation 17.

The duty cycle varies with the bulk input voltage (V_BULK). V_BULK varies from 95V to 375V during normal operation. This causes the duty cycle to vary from 24% to 56%.

Equation 18.

G_CO(f) is an estimate of the control (V_C) to output transfer function, where variable Q is the quality factor.

Equation 19.

The quality factor (Q) is defined by the primary magnetizing inductance change in voltage (S_N) as a function of duty cycle; as well as, the added slope compensation (S_E).

Equation 20.

Equation 21.

Equation 22.

To ensure that the voltage loop is stable, the crossover frequency must be less than one half of the right-half-plane zero frequency (f_RHPZ) of the flyback converter. The right-half-plane zero frequency at the minimum bulk voltage would be roughly 9.8kHz. For this design example the target crossover of the voltage loop is at 1kHz. The actual f_C may be higher or lower than the target.

Equation 23.

Equation 24.

The DC gain of G_CO(f) moves with the bulk input voltage. Resistor R_Z is selected to crossover the voltage loop when input to the converter is at V_BULK(min) and to crossover at 1/5th the maximum crossover frequency.

Equation 25.

Capacitor C_Z is selected to add 45° of phase margin at voltage loop crossover. For this design example a 6.8-nF capacitor was used.

Equation 26.

Capacitor C_P is selected to attenuate the high frequency gain of the control loop.

Equation 27.

G_C(f) is the estimated transfer function of the TL431 compensation.

Equation 28.

T_V(f) is the estimated theoretical transfer function of the close-loop gain of the system. The feedback loop response may be different in the actual circuit and may have to be adjusted with a network analyzer to meet actual circuit performance and reliability. The feedback loop response must be evaluated over worse case variations in design parameters.

Equation 29.

For this application example, this design technique generated a theoretical feedback loop (T_V(f)) crossover at 1kHz with roughly 55° of phase margin at a minimum input bulk voltage of 95V. The theoretical voltage loop at high-line crossed over at 2.7kHz with a phase margin of 72°. See Figure 8-2 and Figure 8-3. T_V(f) must be evaluated with a network analyzer and adjust the loop compensation as necessary based on the actual circuitry behavior. Also conduct transient testing to ensure that the device remains stable.