SLUSG21C May   2025  – August 2026 UCC25661

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Power Proportional Control
        1. 7.3.1.1 Voltage Feedforward
      2. 7.3.2 VCR Synthesizer
        1. 7.3.2.1 TSET Programming
        2. 7.3.2.2 TSET Programming for UCC256616
      3. 7.3.3 Feedback Chain (Control Input)
      4. 7.3.4 Adaptive Dead-Time
      5. 7.3.5 Input Voltage Sensing
        1. 7.3.5.1 Brownin and Brownout Thresholds and Options
        2. 7.3.5.2 AC Input Zero Crossing Detection
        3. 7.3.5.3 Output OVP and External OTP
      6. 7.3.6 Resonant Tank Current Sensing
    4. 7.4 Protections
      1. 7.4.1 Zero Current Switching (ZCS) Protection
      2. 7.4.2 Minimum Current Turn-off During Soft Start
      3. 7.4.3 Cycle by Cycle Current Limit and Short Circuit Protection
      4. 7.4.4 Overload (OLP) Protection
      5. 7.4.5 VCC OVP Protection
    5. 7.5 Device Functional Modes
      1. 7.5.1 Startup
        1. 7.5.1.1 With HV Start-up
          1. 7.5.1.1.1 First Time Start-up Sequence
          2. 7.5.1.1.2 Restart Sequence
        2. 7.5.1.2 Without HV Startup
      2. 7.5.2 Soft Start Ramp
        1. 7.5.2.1 Startup Transition to Regulation
      3. 7.5.3 Light Load Management
        1. 7.5.3.1 Operating Modes (Burst Pattern)
        2. 7.5.3.2 Mode Transition Management
        3. 7.5.3.3 Burst Mode Thresholds Programming
        4. 7.5.3.4 TSET Pin Alternate Function in Burst Mode
          1. 7.5.3.4.1 PFC On/Off
          2. 7.5.3.4.2 Forced Burst-Mode
        5. 7.5.3.5 Soft On/Off
      4. 7.5.4 X-Capacitor Discharge
        1. 7.5.4.1 Detecting Through HV Pin Only
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 Design Considerations for Adaptive Dead-Time
        13. 8.2.2.13 LLC Rectifier Diodes
        14. 8.2.2.14 LLC Output Capacitors
        15. 8.2.2.15 HV Pin Series Resistors
        16. 8.2.2.16 BLK Pin Voltage Divider
        17. 8.2.2.17 ISNS Pin Differentiator
        18. 8.2.2.18 TSET Pin
        19. 8.2.2.19 OVP/OTP Pin
        20. 8.2.2.20 Burst Mode Programming
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VCCP Pin Capacitor
      2. 8.3.2 Boot Capacitor
      3. 8.3.3 V5P Pin Capacitor
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Schematics
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 11.1 Mechanical Data

7.3.2.1 TSET Programming

The voltage programmed for VTSETB voltage configures the minimum operating frequency for IPPC operation and the maximum dead time. In the table TSET voltage values indicated are nominal values. Maximum and minimum range used for each TSET setting is within ± 48mV from nominal value.

Table 7-1 TSET Programming Options to select minimum frequency for IPPC operation
TSET OPTION NUMBERTSET VOLTAGE (VSETB) (V) FOR 3.5V OCPMINIMUM FREQUENCY FOR IPPC OPERATION (kHz)MAXIMUM DEAD-TIME (μs)
172.295698.60.5
162.168591.60.5
152.0415010.5
141.914424.30.5
131.787359.31
121.66304.31
111.533256.71
101.416218.21
91.299184.81
81.182156.51
71.074132.51
60.967112.21
50.850951
40.74280.51
30.64468.11
20.54757.71
10.45048.91
X(1)< 0.392——
(1) Not recommended for use.
The difference between VTSETA and VTSETB configures the integrator time constants that set the FBReplica magnitude for a given power output, enabling setting the overload power (OLP) thresholds.
Table 7-2 TSET Programming Options to Select Integrator Time Constant
TSET OPTION NUMBER TSET VOLTAGE(VTSETA-VTSETB) (V) FOR 3.5V OCP INTEGRATOR TIME CONSTANT (ns)
17 2.295 68
16 2.168 80
15 2.041 93
14 1.914 112
13 1.787 132
12 1.66 156
11 1.533 184
10 1.416 214
9 1.299 257
8 1.182 304
7 1.074 359
6 0.967 424
5 0.850 490
4 0.742 588
3 0.644 694
2 0.547 820
1 0.450 968
X(1) < 0.392 X
  1. Not recommended for use.