2 Single-Event Effects (SEE)

The CDCLVP111-SEP device does not operate at high voltages or high currents; therefore, single-event burn-out (SEB) and single-event gate-rupture (SEGR) events are not expected issues. The primary single-event effect (SEE) events of interest in the CDCLVP111-SEP are single-event latch-up (SEL) and single-event transient (SET).

From a risk and impact point-of-view, the occurrence of an SEL is potentially the most destructive SEE event and the biggest concern for space applications. In mixed technologies, such as the Linear RF-SiGe process used for the CDCLVP111-SEP, the CMOS circuitry introduces a potential SEL susceptibility. SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure that is formed between the p-substrate and n-well as well as the n+ and p+ contacts (Shoga; Binder 1986 and Bruguier; Palau 1996). The parasitic bipolar structure creates a high-conductance path (creating a steady-state current that is typically orders-of-magnitude higher than the normal operating current) between the power and ground that persists (is latched) until the power is removed or until the device is destroyed by the high-current state. The process modifications applied for SEL-mitigation are sufficient, as the CDCLVP111-SEP exhibits no SEL with heavy-ions of LET_EFF = 47.5MeVcm² /mg at a fluence of 10⁷ ions/cm2 and a chip temperature of 125°C.

As the functional block diagram in Figure 2-1 shows, SETs can potentially affect the CDCLVP111-SEP in one of two primary ways:

• Local-creating temporary upsets that affect just one pair at a time
• Global-creating temporary upsets that affects all ten output pairs at a time

The global SET can be generated in the input buffers circuitry, which disrupts the currently-selected clock or affects the multiplexer select line and can potentially cause either a disruption of the clock pulse or a temporary switch to the wrong input clock. To be able to distinguish if this fail mode has occurred, set the two input clocks to different frequencies (a sudden change in clock frequency reveals that such an event has occurred). No such events were observed in any of the tests. The SET impacts the buffers in such a way that the affected clock line exhibits a positive, negative, or bipolar clock pulse disturbance whose magnitude, polarity, and duration depend on how the ionization from the SET is distributed (a function of the ion LET, location, trajectory, energy, the thickness and composition of the back-end-of-line (BEOL) stack, and so forth) and what part of the circuit is hit. The actual shape and duration of the SETs is a strong function of output capacitance and the load conditions, as well. Ultimately, SETs are only a concern if their magnitude and duration actually cause an erroneous clock pulse (extra clock pulse) or a missing clock pulse disruption which impacts the down-stream circuitry. All the observed SETs either increased or narrowed a single pulse width, created a missing pulse, or created a smaller single (runt) pulse.

Figure 2-1 Functional Block Diagram of CDCLVP111-SEP