SLVSGF0B October   2022  – March 2025 TPS3435-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Timeout Watchdog Timer
        1. 7.3.1.1 tWD Timer
        2. 7.3.1.2 Watchdog Enable Disable Operation
        3. 7.3.1.3 tSD Watchdog Start Up Delay
        4. 7.3.1.4 SET Pin Behavior
      2. 7.3.2 Manual RESET
      3. 7.3.3 WDO Output
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Assert Delay
        1. 8.1.1.1 Factory-Programmed Output Assert Delay Timing
        2. 8.1.1.2 Adjustable Capacitor Timing
      2. 8.1.2 Watchdog Timer Functionality
        1. 8.1.2.1 Factory-Programmed Timing Options
        2. 8.1.2.2 Adjustable Capacitor Timing
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Monitoring a Standard Microcontroller for Timeouts
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Setting the Watchdog Timeout Period
          2. 8.2.1.2.2 Setting Output Assert Delay
          3. 8.2.1.2.3 Setting the Startup Delay
          4. 8.2.1.2.4 Calculating the WDO Pullup Resistor
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.1.1 Design Requirements

PARAMETERDESIGN REQUIREMENTDESIGN RESULT
Watchdog Timeout PeriodTypical timeout period of 40msTypical timeout period of 40ms
Watchdog Output Assert DelayTypical output assert of 2msTypical output assert of 2ms
Startup DelayMinimum startup delay of 700msMinimum startup delay of 900ms
Output logic voltageOpen-drainOpen-drain
Maximum device current consumption20µA250nA typical, 3.0μA maximum(1)
(1) Only includes the current consumption of the TPS3435-Q1.