SLVSGF0B October   2022  – March 2025 TPS3435-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Timeout Watchdog Timer
        1. 7.3.1.1 tWD Timer
        2. 7.3.1.2 Watchdog Enable Disable Operation
        3. 7.3.1.3 tSD Watchdog Start Up Delay
        4. 7.3.1.4 SET Pin Behavior
      2. 7.3.2 Manual RESET
      3. 7.3.3 WDO Output
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Assert Delay
        1. 8.1.1.1 Factory-Programmed Output Assert Delay Timing
        2. 8.1.1.2 Adjustable Capacitor Timing
      2. 8.1.2 Watchdog Timer Functionality
        1. 8.1.2.1 Factory-Programmed Timing Options
        2. 8.1.2.2 Adjustable Capacitor Timing
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Monitoring a Standard Microcontroller for Timeouts
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Setting the Watchdog Timeout Period
          2. 8.2.1.2.2 Setting Output Assert Delay
          3. 8.2.1.2.3 Setting the Startup Delay
          4. 8.2.1.2.4 Calculating the WDO Pullup Resistor
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

At 1.04V ≤ VDD ≤ 6V, MR = Open, WDO pull-up resistor (Rpull-up) = 100kΩ to VDD, output load (CLOAD) = 10pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1V/µs. Typical values are at TA = 25℃
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON PARAMETERS
VDD Input supply voltage Active LOW output 1.04 6 V
IDD Supply current into VDD pin (1) TA = –40℃ to 85℃  0.25 0.8 µA
0.25 3
VIL Low level input voltage WD–EN, WDI, SETx, MR(1) 0.3VDD V
VIH High level input voltage WD–EN, WDI, SETx, MR(1) 0.7VDD V
RMR Manual reset internal pull-up resistance 100 kΩ
WDO (Open-drain active-low)
VOL Low level output voltage
 		 VDD =1.5V
IOUT(Sink) = 500µA		 300 mV
VDD = 3.3V
IOUT(Sink) = 2mA		 300
Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6V
TA = –40℃ to 85℃		 10 30 nA
VDD = VPULLUP = 6V 10 60 nA
WDO (Push-pull active-low)
VPOR Power on WDO voltage (2) VOH(min) = 0.8 VDD
Iout (source) = 15µA		 900 mV
VOL Low level output voltage
 		 VDD = 1.5V
IOUT(Sink) = 500µA		 300 mV
VDD = 3.3V
IOUT(Sink) = 2mA		 300
VOH High level output voltage
 		 VDD = 1.8V
IOUT(Source) = 500µA		 0.8VDD V
VDD = 3.3V
IOUT(Source) = 500µA		 0.8VDD
VDD = 6V
IOUT(Source) = 2mA		 0.8VDD
(1) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
(2) VPOR is the minimum VDD voltage level for a controlled output state