SLVSH58B November   2024  – January 2025 DRV81004-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
      1. 5.5.1 SPI Timing Requirements
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Control Pins
        1. 6.3.1.1 Input Pins
        2. 6.3.1.2 nSLEEP Pin
      2. 6.3.2 Power Supply
        1. 6.3.2.1 Modes of Operation
          1. 6.3.2.1.1 Power-up
          2. 6.3.2.1.2 Sleep mode
          3. 6.3.2.1.3 Idle mode
          4. 6.3.2.1.4 Active mode
          5. 6.3.2.1.5 Limp Home mode
          6. 6.3.2.1.6 Reset condition
      3. 6.3.3 Power Stage
        1. 6.3.3.1 Switching Resistive Loads
        2. 6.3.3.2 Inductive Output Clamp
        3. 6.3.3.3 Maximum Load Inductance
        4. 6.3.3.4 Switching Channels in parallel
      4. 6.3.4 Protection and Diagnostics
        1. 6.3.4.1 Undervoltage on VM
        2. 6.3.4.2 Overcurrent Protection
        3. 6.3.4.3 Over Temperature Protection
        4. 6.3.4.4 Over Temperature Warning
        5. 6.3.4.5 Over Temperature and Overcurrent Protection in Limp Home mode
        6. 6.3.4.6 Reverse Polarity Protection
        7. 6.3.4.7 Over Voltage Protection
        8. 6.3.4.8 Output Status Monitor
      5. 6.3.5 SPI Communication
        1. 6.3.5.1 SPI Signal Description
          1. 6.3.5.1.1 Chip Select (nSCS)
            1. 6.3.5.1.1.1 Logic high to logic low Transition
            2. 6.3.5.1.1.2 Logic low to logic high Transition
          2. 6.3.5.1.2 Serial Clock (SCLK)
          3. 6.3.5.1.3 Serial Input (SDI)
          4. 6.3.5.1.4 Serial Output (SDO)
        2. 6.3.5.2 Daisy Chain Capability
        3. 6.3.5.3 SPI Protocol
        4. 6.3.5.4 SPI Registers
          1. 6.3.5.4.1  Standard Diagnosis Register
          2. 6.3.5.4.2  Output control register
          3. 6.3.5.4.3  Input 0 Mapping Register
          4. 6.3.5.4.4  Input 1 Mapping Register
          5. 6.3.5.4.5  Input Status Monitor Register
          6. 6.3.5.4.6  Open Load Current Control Register
          7. 6.3.5.4.7  Output Status Monitor Register
          8. 6.3.5.4.8  Configuration Register
          9. 6.3.5.4.9  Output Clear Latch Register
          10. 6.3.5.4.10 Configuration Register 2
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Typical Application
      2. 7.1.2 Suggested External Components
      3. 7.1.3 Application Plots
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Package Footprint Compatibility
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.1 Overview

The DRV81004-Q1 is a four-channel low-side switch providing integrated protection and diagnostic functions. The output stages incorporate four N-channel power MOSFET low-side switches (typical RDS(ON) at TJ = 25 °C is 700mΩ). The DRV81004-Q1 is designed for low-supply voltage operation. It can keep its state at a low battery voltage (VM ≥ 3V).

The 16-bit SPI interface is used to control and diagnose the device and the loads. The SPI interface supports a daisy chain in order to connect multiple devices (also devices with 8-bit SPI) in one SPI chain by using the same microcontroller pins. The SPI feature is available only when the digital power supply is present.

The DRV81004-Q1 has two input pins that are connected to two outputs. When nSLEEP pin is logic low, it is possible to activate channels 2 and 3 using the input pins independently from the availability of the digital supply voltage. With the Input Mapping feature, it is possible to connect the input pins to different outputs or assign more outputs to the same input pin. In this case, more channels can be controlled with one input signal.

In Limp Home mode, the input pins are directly routed to channels 2 and 3. When nSLEEP pin is logic low, it is possible to activate the two channels using the input pins independently from the presence of the digital supply voltage.

The device provides the diagnosis of the load via Open Load (in OFF state) and short circuit detection. For Open Load detection, an internal current source can be activated via SPI. Each output stage is protected against short circuits. In case of overcurrent, the affected channel switches OFF when the overcurrent detection threshold is reached and can be reactivated via SPI.

In Limp Home mode operation, the channels connected to an input pin are set to logic high restart automatically after output restart time elapses. Temperature sensors are available for each channel to protect the device against overtemperature.

Table 6-1 Product Summary

Parameter

Symbol

Values
Analog supply voltage

VM

3.0V to 40V

Digital supply voltage

VDD

3.0V to 5.5V
Minimum overvoltage protection

VM_AZ

42V

Maximum on-state resistance at TJ = 150 °C

RDS(ON)

1.4Ω
Nominal load current (TA = 85 °C, all channels)

IL_NOM

470mA
Maximum Energy dissipation - repetitive

EAR

10mJ @ IL_EAR = 220mA
Minimum Drain to Source clamping voltage

VDS_CL

42V
Maximum overload switch OFF threshold

IL_OVL0

2.1A or 3A

Maximum total quiescent current at TJ ≤ 85 °C

ISLEEP

2.7μA

Maximum SPI clock frequency

fSCLK

5MHz